FinFET Backside Power Rail Layout for Lower Voltage Drop
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Solution Overview
Problem
Conventional integrated circuits face increased voltage drop and power consumption as they scale down, due to inefficiencies in power rail design and interconnectivity, which are not adequately addressed by existing semiconductor fabrication methods.
Innovation Solution
The implementation of backside power rails and self-aligned vias in FinFET devices, which allows for wider metal tracks and increased gate density, reducing power rail resistance and enhancing device integration by isolating power rails from nearby conductors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If power rails are scaled down with integrated circuits, then device integration is improved, but voltage drop across power rails increases
Solution Approach 1:
The patent introduces backside power rails on the rear surface of the semiconductor substrate, transitioning power rail placement from a two-dimensional planar arrangement to a three-dimensional configuration that utilizes the substrate thickness dimension. This allows power rails to be positioned closer to transistor sources and drains without occupying front-side area, reducing voltage drop while maintaining high device integration density on the front side.
Solution Approach 2:
The power delivery system is segmented into separate front-side interconnect structures and back-side power rails. This segmentation allows independent optimization of each component: front-side structures handle signal routing and transistor placement, while back-side structures provide dedicated low-resistance power delivery paths directly to transistor contacts, reducing overall voltage drop.
2Area of stationary object
If power rails are scaled down with integrated circuits, then area is reduced, but power consumption increases
Solution Approach 1:
By moving power rails to the backside of the substrate and utilizing the vertical dimension through self-aligned vias, the patent reduces the lateral area occupied by power rails on the front side while creating direct, low-resistance vertical paths for current flow. This reduces I²R losses and overall power consumption without increasing the chip area.
Solution Approach 2:
Self-aligned vias act as intermediary conductive structures that directly connect backside power rails to front-side transistor sources and drains. These vias provide low-resistance vertical interconnect paths that minimize power loss, enabling efficient power delivery through the substrate thickness without requiring large lateral power rail areas.
3Loss of energy
If backside power rails are implemented, then power rail resistance is reduced, but device complexity increases
Solution Approach 1:
The fabrication process uses self-aligned techniques where previously formed structures serve as alignment references for subsequent steps. The backside power rails are self-aligned to front-side transistor contacts through the substrate, eliminating the need for separate alignment operations and reducing the complexity increase despite adding new structures.
Solution Approach 2:
The patent performs preliminary actions during front-side fabrication by forming via holes and depositing conductive materials that will later serve as alignment references for backside power rail formation. This preliminary structuring simplifies the backside processing by providing pre-defined alignment targets, reducing overall fabrication complexity.
Data Source
AI summary
A semiconductor structure includes a power rail on a back side of the semiconductor structure, a first interconnect structure on a front side of the semiconductor structure, and a source feature, a drain feature, a first semiconductor fin, and a gate structure that are between the power rail and the first interconnect structure. The first semiconductor fin connects the source feature and the drain feature. The gate structure is disposed on a front surface and two side surfaces of the first semiconductor fin. The semiconductor structure further includes an isolation structure disposed between the power rail and the drain feature and between the power rail and the first semiconductor fin and a via penetrating through the isolation structure and connecting the source feature to the power rail.