Fin-FET Devices With Barrier Structures To Reduce Parasitic Capacitance
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Solution Overview
Problem
Existing Fin-FET devices face challenges in improving electrical performance due to insufficient controllability of channel current and increased parasitic capacitance, which affects the stress in the channel region and the growth rate of source/drain regions.
Innovation Solution
A method for fabricating Fin-FET devices involves forming a fin structure on a semiconductor substrate with a core region and peripheral regions, using dummy gate structures and barrier structures to control the growth of source/drain regions, and replacing the dummy gate electrode layers with metal gate structures while maintaining the barrier structures to reduce parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If dummy gate structures are used to control source/drain growth, then uniform growth is achieved, but parasitic capacitance increases
Solution Approach 1:
The patent removes the dummy gate electrode layer in peripheral regions while retaining barrier structures, extracting the harmful parasitic capacitance source while preserving the beneficial growth control function. This selective removal reduces parasitic capacitance between dummy gates and source/drain regions while maintaining uniform source/drain growth through the retained barrier structures.
Solution Approach 2:
The patent applies different structures to different regions: core regions retain both dummy gate electrode layers and barrier structures for precise growth control, while peripheral regions keep only barrier structures to minimize parasitic capacitance. This local differentiation optimizes both uniformity and parasitic reduction in their respective zones.
2Manufacturing precision
If barrier structures are formed in peripheral regions, then source/drain growth is controlled, but device complexity increases
Solution Approach 1:
The barrier structures serve multiple functions: they control source/drain growth in peripheral regions, maintain stress in channel regions, and reduce parasitic capacitance when dummy gates are removed. This multi-functionality reduces the need for separate structures, thereby managing complexity while achieving multiple objectives.
Solution Approach 2:
The patent combines the growth control function with the stress maintenance function into a single barrier structure, eliminating the need for separate structures. The barrier structure simultaneously prevents source/drain growth in peripheral regions and maintains mechanical stress in the channel, reducing overall device complexity.
3Reliability
If metal gate structures replace dummy gate electrode layers, then electrical performance improves, but manufacturing steps increase
Solution Approach 1:
The patent forms barrier structures before removing dummy gate electrode layers and forming metal gates. This preliminary action ensures that source/drain regions are properly controlled and stress is maintained before the critical metal gate formation step, facilitating a smoother manufacturing process despite the additional steps.
Solution Approach 2:
The patent segments the device into core regions and peripheral regions, allowing different manufacturing approaches in each zone. Core regions undergo complete metal gate formation for high performance, while peripheral regions retain simplified structures, enabling selective optimization and managing overall manufacturing complexity.
Data Source
AI summary
A Fin-FET device is provided. The Fin-FET device includes a semiconductor substrate, a fin structure formed on the semiconductor substrate having a core region and two peripheral regions separated by the core region; a plurality of metal gate structures formed across the fin structure in the core region and covering top and sidewall surfaces of the fin structure; a barrier structure formed in each peripheral region across the fin structure and covering top and sidewall surfaces of the fin structure; a plurality of source/drain regions formed in the fin structure between each barrier structure and a neighboring metal gate structure and between neighboring metal gate structures; and a first interlayer dielectric layer formed at least on the fin structure. The first interlayer dielectric layer covers sidewall surfaces of the metal gate structures and the barrier structures.