FinFET Source/Drain Barrier Structure for Dopant Diffusion Control
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Solution Overview
Problem
The increasing demand for high-performance, high-speed, and multifunctional semiconductor devices necessitates the development of semiconductor devices with fine patterns and reduced operating characteristics limitations due to size reduction, particularly in planar metal oxide semiconductor FETs, which can be addressed by incorporating a FinFET with a three-dimensional channel structure.
Innovation Solution
A semiconductor device design featuring a substrate with an active region, gate structures intersecting the active region, and source/drain regions with specific layer configurations, including a first semiconductor layer, diffusion barrier layers containing carbon, and a second semiconductor layer, which prevent dopant diffusion and enhance reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the channel width is reduced to achieve fine patterns, then the manufacturing precision is improved, but the short channel effects worsen
Solution Approach 1:
The patent transitions from a planar channel structure to a three-dimensional FinFET channel structure. The channel extends in the vertical dimension (thickness direction) in addition to the horizontal plane, creating a fin-like protrusion. This dimensional change allows the channel to maintain effective width for fine patterning while gaining vertical control through the gate, thereby suppressing short channel effects that plague scaled-down planar devices.
Solution Approach 2:
The channel is segmented into multiple portions along the thickness direction, with different semiconductor materials used in different segments. This segmentation allows optimization of each segment's properties - the lower channel portion can be designed for strong gate control and the upper portion for carrier transport, thereby maintaining reliability while achieving fine pattern dimensions.
2Ease of manufacture
If the planar structure is used to simplify manufacturing, then the ease of manufacture is improved, but the device complexity increases due to short channel effects
Solution Approach 1:
By introducing the vertical dimension through FinFET structure, the patent achieves better electrostatic control without significantly complicating the manufacturing process. The vertical fin structure can be formed using standard semiconductor fabrication techniques such as selective epitaxial growth or deposition, followed by gate formation, making the transition from planar to FinFET relatively straightforward while dramatically improving device performance.
3Ease of manufacture
If dopant diffusion is allowed to simplify the doping process, then the ease of manufacture is improved, but the reliability deteriorates due to dopant contamination
Solution Approach 1:
The patent introduces a diffusion barrier layer as an intermediary between the source/drain region and the channel. This barrier layer, positioned at the interface, prevents direct dopant diffusion from the source/drain into the channel while still allowing the doping process to proceed. The barrier layer acts as a mediator that blocks harmful dopant migration while maintaining the simplicity of the overall doping工艺流程.
Solution Approach 2:
The channel structure employs composite materials with different semiconductor properties in different regions. By using materials with appropriate band offsets and diffusion characteristics in the channel and barrier layer, the patent achieves effective dopant blocking without requiring complex doping processes. The composite material structure inherently prevents dopant contamination while maintaining manufacturing simplicity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design improves the reliability of semiconductor devices by preventing dopant diffusion and reducing short channel effects, thereby enhancing performance and stability.
Implementation Method 1
a diffusion barrier layer on an upper region of the first semiconductor layer and including carbon
Data Source
AI summary
A semiconductor device is provided. The semiconductor device includes: a substrate including an active region; a gate structure intersecting the active region on the substrate; channel layers on the active region, spaced apart from each other and surrounded by the gate structure; and a source/drain region on the active region adjacent the gate structure and connected to the plurality of channel layers. The source/drain region includes: a first semiconductor layer on side surfaces of the channel layers; a diffusion barrier layer on an upper region of the first semiconductor layer and including carbon, wherein an upper surface of a first channel layer that is a lowermost channel layer among the plurality of channel layers is provided between the substrate and a lower end of the diffusion barrier layer; and a second semiconductor layer on the diffusion barrier layer and the first semiconductor layer.