FinFET Channel Barrier Layer to Reduce Dopant Migration
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Solution Overview
Problem
The scaling down of semiconductor integrated circuits (ICs) to smaller geometries increases complexity and cost due to the complexity of processing and manufacturing, particularly with the use of FinFET transistors, which requires more sophisticated and costly fabrication processes.
Innovation Solution
A method for fabricating a semiconductor device that includes forming a barrier layer between the channel and well in a FinFET transistor, using either silicon oxide or silicon carbide, which reduces dopant migration and improves transistor performance by enhancing drain-induced barrier lowering (DIBL), effective drain current, and active power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If FinFET transistors are used to achieve smaller geometry sizes, then production efficiency increases and costs decrease, but process complexity and manufacturing complexity increase significantly
Solution Approach 1:
The channel region is segmented into multiple doped regions (first doped region, second doped region, third doped region) with different dopant types and concentrations. This segmentation allows independent optimization of each region's electrical characteristics, enabling FinFET performance improvement without requiring overly complex processing steps.
Solution Approach 2:
Different dopant concentrations and types are applied to different spatial locations within the channel. The first doped region has a first dopant concentration, the second doped region has a second dopant concentration, and the third doped region has a third dopant concentration. This local quality variation optimizes carrier transport and electric field distribution locally, achieving high performance with manageable process complexity.
2Reliability
If doping concentration in the channel is increased to improve transistor performance, then effective drain current increases, but dopant migration increases which degrades device reliability
Solution Approach 1:
An undoped or lightly-doped fourth doped region is introduced as an intermediary between the heavily doped source/drain regions and the channel. This intermediary region acts as a buffer that prevents direct dopant diffusion from high-concentration regions into the channel, thereby reducing dopant migration while maintaining the beneficial high doping concentrations in the source and drain regions for high current drive.
Solution Approach 2:
The fourth doped region serves as a sacrificial buffer zone that can be heavily doped temporarily during manufacturing to enable subsequent dopant diffusion processes, then later removed or modified through annealing or additional doping steps. This disposable region enables complex doping profiles to be achieved through simpler sequential processing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method reduces dopant migration by up to 58%, improves DIBL from 10 to 15 mV, increases effective drain current by 5-8%, and enhances power-frequency performance by 0.5-1.5%, thereby simplifying and reducing the cost of fabricating FinFET transistors while maintaining performance.
Implementation Method 1
reduces dopant migration
Data Source
AI summary
A method for fabricating a semiconductor device includes receiving a silicon substrate having an isolation feature disposed on the substrate and a well adjacent the isolation feature, wherein the well includes a first dopant. The method also includes etching a recess to remove a portion of the well and epitaxially growing a silicon layer (EPI layer) in the recess to form a channel, wherein the channel includes a second dopant. The method also includes forming a barrier layer between the well and the EPI layer, the barrier layer including at least one of either silicon carbon or silicon oxide. The barrier layer can be formed either before or after the channel. The method further includes forming a gate electrode disposed over the channel and forming a source and drain in the well.