FinFET Barrier Layer Radical Oxidation for Stress Quality
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Solution Overview
Problem
The challenge in semiconductor manufacturing is the difficulty in controlling the channel regions of FinFETs due to the decreasing channel length, leading to subthreshold leakage and poor quality of embedded SiGe stress layers, which affects the carrier mobility and overall performance of FinFETs.
Innovation Solution
A method involving the formation of a barrier layer on the fins, conversion of its top portion to a passive layer through radical oxidation, followed by an etch-back process to form passive sidewalls, and subsequent removal of the remaining barrier layer using a wet etching process to prevent stress layer bridging and enhance the quality of the SiGe structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the channel length of MOSFETs is continuously decreased to increase integration level and switch speed, then the integration level and switch speed are improved, but the control ability of gate structures to channel regions deteriorates, leading to subthreshold leakage
Solution Approach 1:
The patent transitions from planar MOSFETs to three-dimensional FinFETs, utilizing vertical fins to extend the gate control into the third dimension. This dimensional change allows the gate to control the channel from multiple surfaces, effectively improving gate control ability despite continued channel length reduction.
Solution Approach 2:
The channel region is segmented into multiple fins, with each fin providing an independent pathway for carrier flow. This segmentation allows the gate to control each fin individually, maintaining effective control even as overall device dimensions are reduced.
2Reliability
If embedded SiGe structures are formed to increase carrier mobility, then the drive current is improved, but the quality of stress layers deteriorates due to existing formation methods
Solution Approach 1:
A barrier layer is formed on the fin surfaces before forming the SiGe stress layer. This preliminary action prevents unwanted SiGe deposition on surfaces where it would be harmful, ensuring high-quality stress layers only where needed while maintaining excellent carrier mobility enhancement.
Solution Approach 2:
The barrier layer is selectively positioned only on specific surfaces (fin top and sidewalls) rather than uniformly across the entire structure. This local quality approach allows SiGe stress layers to be formed with high precision only in regions where stress enhancement is beneficial, preventing bridging and maintaining manufacturing quality.
3Manufacturing precision
If a barrier layer is formed to prevent stress layer bridging, then the manufacturing precision is improved, but the process complexity increases due to additional formation steps
Solution Approach 1:
The barrier layer serves multiple functions simultaneously: it prevents stress layer bridging, provides a foundation for selective SiGe deposition, and can be integrated with existing gate or isolation layer processes. This multi-functionality reduces the need for separate dedicated barrier formation steps, managing process complexity.
Solution Approach 2:
The barrier layer formation is merged with existing process steps in the fabrication sequence, such as combining it with gate formation or fin isolation processes. This merging approach integrates the barrier layer creation into the overall manufacturing flow without requiring entirely separate process equipment or steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures smooth and even top surfaces of the fins, preventing 'V' shape trenches and improving the quality of stress layers, thereby enhancing the electrical properties and performance of FinFETs by maintaining the integrity of the barrier layer on the side surfaces.
Implementation Method 1
performing a radical oxidation process to convert a top portion of the barrier layer to a passive layer
Data Source
AI summary
A method for forming FinFETs includes, sequentially, providing a substrate; forming a plurality of fins on a surface of the substrate; forming a gate structure overlying on at least one of the plurality of fins; forming a barrier layer covering top and side surfaces of the gate structures, and top and side surfaces of the plurality of fins; performing a radical oxidation process to convert a top portion of the barrier layer to a passive layer to form a remaining barrier layer and to cause the top surfaces of the fins to be flat after subsequent etching processes; performing an etch-back process on the passive layer to form passive sidewalls on side surfaces of the portions of the remaining barrier on the side surfaces of the fins; and removing portions of the remaining barrier layer on the top surfaces of the fins by a wet etching process using the passive sidewalls as an etching mask.