FinFET Gate Structure in Bent Trench Feature for Dual Stress
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Solution Overview
Problem
Current methods for selectively applying tensile and compressive stresses to N-type and P-type semiconductor devices require complex processing steps and specific materials, leading to increased manufacturing costs and only moderate stress levels, which limits the performance enhancement of both device types.
Innovation Solution
The method involves forming a semiconductor structure with a bend and a trench feature, where thermal oxidation is used to induce dual stresses in silicon-on-insulator (SOI) substrates, creating compressive stress in one region and tensile stress in another, allowing for improved mobility of NFETs and PFETs by positioning the gate structure within the stress-induced regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If trench isolation structure or liners are used to selectively apply stress, then stress can be applied to N type and P type devices, but the processing steps become more complicated and manufacturing costs increase
Solution Approach 1:
The patent merges the stress application for both N type and P type devices into a single unified process. By forming one continuous trench isolation structure across the substrate and selectively positioning NFETs and PFETs in different stress regions (tensile and compressive respectively), the invention eliminates the need for separate trench isolation structures or liner deposition steps for each device type, thereby reducing processing complexity while maintaining selective stress application
Solution Approach 2:
The trench isolation structure serves multiple functions simultaneously: it provides electrical isolation between devices, defines device regions, and creates differential stress fields. By making the trench isolation structure multi-functional, the invention eliminates the need for additional dedicated stress application structures, reducing overall device complexity while achieving selective stress application
2Reliability
If trench isolation structure or liners are used to apply stress, then stress can be induced in channel regions, but only moderate stress levels (hundreds of MPa) are achieved
Solution Approach 1:
The patent changes the physical and chemical parameters of the trench isolation structure to enhance stress levels. By controlling the trench depth, fill material composition, and thermal processing parameters during oxidation, the invention generates significantly higher stress levels in the channel regions compared to conventional approaches, thereby improving device performance through enhanced carrier mobility
3Ease of manufacture
If the same stress component is applied to both N type and P type devices, then the manufacturing process is simplified, but the performance of one device type is degraded
Solution Approach 1:
The patent applies local quality by creating different stress conditions in different spatial regions of the substrate. The trench isolation structure is designed to generate tensile stress in regions where NFETs are formed and compressive stress in regions where PFETs are formed. This allows each device type to receive its optimal stress component for maximum performance while using a single unified manufacturing process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively enhances the mobility of both N-type and P-type devices by applying significant dual stresses, improving device performance while simplifying the manufacturing process and reducing costs.
Implementation Method 1
thermal oxidation is used to induce dual stresses in silicon-on-insulator (SOI) substrates
Implementation Method 2
thermal oxidation is used to induce dual stresses in silicon-on-insulator (SOI) substrates, creating compressive stress in one region and tensile stress in another
Data Source
AI summary
A semiconductor device including semiconductor material having a bend and a trench feature formed at the bend, and a gate structure at least partially disposed in the trench feature. A method of fabricating a semiconductor structure including forming a semiconductor material with a trench feature over a layer, forming a gate structure at least partially in the trench feature, and bending the semiconductor material such that stress is induced in the semiconductor material in an inversion channel region of the gate structure.