Sublithographic FinFETs via Block Copolymer Self-Assembly
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Solution Overview
Problem
FinFET structures face challenges in scaling down to sublithographic fin widths and achieving optimal minority carrier mobility due to lithographic limitations and the need for specific crystallographic surface orientations for p-type and n-type transistors.
Innovation Solution
The use of self-aligned self-assembly polymers to form sublithographic width semiconductor fins with optimized surface orientations for p-type and n-type finFETs, employing block copolymers to create parallel polymer block lines that serve as etch masks for patterning semiconductor fins with enhanced carrier mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional lithography is used to pattern finFET structures, then manufacturing process is straightforward, but fin width cannot be scaled down below lithographic resolution limits
Solution Approach 1:
The patent applies segmentation by dividing the fin formation process into multiple stages: first forming a mandrel pattern at lithographic resolution, then using self-assembling block copolymers to create finer sub-lithographic features. This multi-stage segmentation enables fin widths below the lithographic resolution limit while maintaining manufacturing feasibility.
Solution Approach 2:
The patent transitions from two-dimensional lithographic patterning to three-dimensional self-assembly of block copolymers. By utilizing the vertical dimension and self-organizing properties of block copolymer layers, the process achieves sub-lithographic fin width precision that cannot be obtained through conventional planar lithography alone.
2Reliability
If fin width is reduced to improve short channel control, then device performance improves, but manufacturing precision requirements increase beyond lithographic capabilities
Solution Approach 1:
The patent employs self-service by utilizing the inherent self-assembling properties of block copolymers to automatically form uniform sub-lithographic patterns. The block copolymer system self-organizes into regular structures with controlled dimensions, eliminating the need for external intervention to achieve the precise fin width required for improved short channel control.
Solution Approach 2:
The patent changes the physical and chemical parameters of the patterning system by introducing block copolymers with specific molecular weights, compositions, and self-assembly characteristics. By adjusting these parameters, the process achieves fin width precision beyond conventional lithographic capabilities while maintaining manufacturability.
3Reliability
If single crystal silicon fins are used to ensure good short channel control, then device reliability improves, but minority carrier mobility is limited by crystallographic orientation constraints
Solution Approach 1:
The patent applies local quality by creating different crystallographic orientations in different regions of the semiconductor structure. By controlling the orientation of the semiconductor layer relative to the fin direction, the patent optimizes minority carrier mobility in specific local regions while maintaining overall short channel control through the finFET architecture.
Solution Approach 2:
The patent utilizes composite material structures combining semiconductor layers with specific crystallographic orientations. By stacking semiconductor layers with different orientations or using composite semiconductor materials, the patent achieves both good short channel control and enhanced minority carrier mobility that cannot be obtained with single-orientation silicon alone.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of finFETs with sublithographic widths and optimized surface orientations, improving short channel control and minority carrier mobility, thereby enhancing on-current and switching speed.
Implementation Method 1
employing self-aligned self-assembly polymers to form sublithographic width semiconductor fins with optimized surface orientations
Data Source
AI summary
At least one recessed region having two parallel edges is formed in an insulator layer over a semiconductor layer such that the lengthwise direction of the recessed region coincides with optimal carrier mobility surfaces of the semiconductor material in the semiconductor layer for finFETs to be formed. Self-assembling block copolymers are applied within the at least one recessed region and annealed to form a set of parallel polymer block lines having a sublithographic width and containing a first polymeric block component. The pattern of sublithographic width lines is transferred into the semiconductor layer employing the set of parallel polymer block lines as an etch mask. Sublithographic width semiconductor fins thus formed may have sidewalls for optimal carrier mobility for p-type finFETs and n-type finFETs.