FinFET Block Architecture With Floating Power Buses
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Solution Overview
Problem
The existing design of integrated circuits lacks a flexible finFET block architecture suitable for standard cell libraries, which limits the implementation of finFET-based integrated circuits with efficient layout features and flexible design tools.
Innovation Solution
The development of finFET block structures and standard cell libraries that incorporate flexible layout features, including 'tall' finFET blocks with floating power buses, allowing for the creation of dense and efficient integrated circuits using finFET block architectures within electronic design automation tools.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If traditional planar transistor architecture is used, then manufacturing process is simpler, but layout density and power efficiency are insufficient
Solution Approach 1:
The patent transitions from traditional planar (2D) transistor architecture to three-dimensional finFET architecture, where fins extend vertically from the substrate. This dimensional change enables significantly higher layout density and improved power efficiency while maintaining compatibility with standard manufacturing processes through carefully designed block structures that organize fins into reusable units.
2Adaptability or versatility
If fixed standard cell library architecture is used, then design consistency is maintained, but flexibility for engineering changes is limited
Solution Approach 1:
The patent divides the finFET implementation into discrete, reusable block structures that can be independently configured and combined. Each block contains a defined number of fins and associated routing resources, allowing designers to assemble standard cells with flexible adaptability while maintaining design consistency through standardized interfaces and verification procedures.
3Area of stationary object
If high-density finFET blocks are implemented, then area efficiency improves, but routing flexibility and power bus integration become more difficult
Solution Approach 1:
The patent designs finFET blocks with integrated, multi-functional structures that combine transistor arrays with embedded power bus routing and signal interconnects. The blocks are configured to accommodate both n-type and p-type fins in complementary arrangements, with power buses that can serve multiple cells simultaneously, thereby maintaining area efficiency while simplifying routing integration through standardized, reusable patterns.
Data Source
Figure 1
Figure 2A~2C
Figure 3A~3B
AI summary
A finFET block architecture suitable for use of a standard cell library, is based on an arrangement including a first set of semiconductor fins in a first region of the substrate having a first conductivity type, and a second set of semiconductor fins in a second region of the substrate, the second region having a second conductivity type. A patterned gate conductor layer including gate traces in the first and second regions, arranged over channel regions of the first and second sets of semiconductor fins is used for transistor gates. Patterned conductor layers over the gate conductor layer are arranged in orthogonal layout patterns, and can include a plurality of floating power buses over the fins in the first and second regions.