FinFET Source/Drain Blocking Layer for Region Separation
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Solution Overview
Problem
The increasing demand for high-performance, high-speed, and multifunctional semiconductor devices requires finer patterns and spacings, which existing semiconductor manufacturing technologies struggle to achieve, particularly in the development of FinFETs with three-dimensional channels.
Innovation Solution
The semiconductor device incorporates fin patterns on a substrate with a gate electrode intersecting them, source/drain regions on the upper surfaces, and a blocking layer on the sidewall of one fin pattern, where the source/drain regions have asymmetric shapes and different conductivities, with the blocking layer extending above the surface to suppress lateral growth and prevent contact between source/drain regions of opposite conductivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If source/drain regions are formed with fine widths and spacings to achieve high integration, then device integration density is improved, but manufacturing precision and pattern control become more difficult
Solution Approach 1:
A blocking layer is introduced as an intermediary structure between adjacent source/drain regions. This blocking layer, formed on the sidewall of the fin pattern, prevents unwanted lateral growth and merging of source/drain regions during fabrication, thereby maintaining manufacturing precision while enabling finer patterning for higher integration density.
Solution Approach 2:
The blocking layer is formed in advance before the source/drain regions are fully processed. This preliminary action establishes precise boundaries that control the subsequent formation and lateral growth of source/drain regions, ensuring accurate pattern definition even at reduced dimensions.
2Productivity
If source/drain regions are placed closer together to increase integration, then device density is improved, but the risk of unwanted contact between regions of opposite conductivity increases
Solution Approach 1:
The blocking layer serves as a physical intermediary barrier between source/drain regions of opposite conductivity types (n-type and p-type). By positioning this blocking layer on the fin sidewall, the invention prevents direct contact between adjacent source/drain regions, thereby maintaining electrical isolation and device reliability even when regions are placed closer together for higher density.
Solution Approach 2:
The blocking layer segments the continuous semiconductor structure into electrically isolated regions. This segmentation creates distinct zones with different conductivity types that remain electrically separated, allowing high-density integration while preventing harmful interactions between adjacent regions.
3Reliability
If asymmetric source/drain regions are formed to improve device characteristics, then device performance is improved, but manufacturing complexity increases
Solution Approach 1:
The blocking layer is positioned asymmetrically on only one sidewall of the fin pattern rather than symmetrically on both sidewalls. This asymmetric configuration enables the formation of asymmetric source/drain regions with different dimensions and properties, which can optimize device characteristics such as current drive and threshold voltage, while the blocking layer itself provides a relatively simple fabrication approach.
Data Source
AI summary
A semiconductor device includes fin patterns on a substrate, at least one gate electrode intersecting the fin patterns, source/drain regions on upper surfaces of the fin patterns, and at least one blocking layer on a sidewall of a first fin pattern of the fin patterns, the at least one blocking layer extending above an upper surface of the first fin pattern of the fin patterns, wherein a first source/drain region of the source/drain regions that is on the upper surface of the first fin pattern has an asymmetric shape and is in direct contact with the at least one blocking layer.