FinFET Body Spacer for Parasitic Capacitance Reduction
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Solution Overview
Problem
The challenge in semiconductor technology is the inconsistency in fin height during the manufacturing of FinFETs, leading to performance inconsistencies across integrated circuits and excessive parasitic capacitance due to dielectric between the gate and fin, which prolongs the response time of the device.
Innovation Solution
A method for manufacturing FinFETs involving the formation of a gate stack intersecting two fins on an isolation layer, where the first semiconductor layer is selectively etched to create a lateral recess filled with a dielectric material to form a body spacer, reducing parasitic capacitance and ensuring uniform fin height through epitaxial growth and precise etching control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If fins are formed vertically on a substrate without body spacer, then the device structure is simpler, but parasitic capacitance increases and response time becomes longer
Solution Approach 1:
The fin structure is segmented into two parts: the main fin body and the bottom portion. A body spacer is introduced to separate the gate electrode from the bottom portion of the fin, effectively segmenting the gate-fin interaction region. This segmentation reduces parasitic capacitance between the gate and fin bottom, thereby improving response time without significantly complicating the overall device structure.
2Ease of manufacture
If fins are formed without selective etching and body spacer, then the manufacturing process is simpler, but fin height consistency deteriorates
Solution Approach 1:
A body spacer is formed at the bottom of the fin structure before the gate electrode is deposited. This preliminary action establishes a reference plane and ensures uniform spacing between the gate and fin bottoms across all fins on the wafer. By performing this spacing action in advance, fin height consistency is improved without requiring complex post-processing adjustments.
Solution Approach 2:
The body spacer acts as an intermediary element between the substrate and the gate electrode. It provides a uniform spacing reference that mediates the relationship between the gate and fin structures, ensuring consistent fin heights across the wafer. This intermediary structure simplifies the manufacturing process by providing a physical reference for subsequent processing steps.
3Object-generated harmful factors
If body spacer is formed with selective etching, then parasitic capacitance is reduced, but manufacturing complexity increases
Solution Approach 1:
The body spacer changes the physical parameters of the gate-fin interface by introducing a dielectric material between the gate electrode and fin bottom. This parameter change reduces the capacitance value at the interface, thereby reducing parasitic capacitance. The selective etching process creates the necessary space for the body spacer, and while it adds a process step, the overall device performance is significantly improved.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the uniformity of fin height and reduces parasitic capacitance, resulting in improved performance consistency and response time of FinFET devices.
Implementation Method 1
selectively etching the first semiconductor layer of the initial fin to form a lateral recess in the first semiconductor layer
Implementation Method 2
filling the lateral recess with a dielectric material to form a body spacer
Implementation Method 3
forming an isolation layer on the substrate, wherein the isolation layer partially exposes the body spacer, and thus defines a fin above the isolation layer
Implementation Method 4
forming a gate stack intersecting the fins on the isolation layer
Data Source
AI summary
A semiconductor device and a method of manufacturing the same are disclosed. In one aspect, the method includes forming a first semiconductor layer and a second semiconductor layer sequentially on a substrate. The method also includes patterning the second and first semiconductor layers to form an initial fin. The method also includes selectively etching the first semiconductor layer of the initial fin to form a lateral recess in the first semiconductor layer. The method also includes filling the lateral recess with a dielectric material to form a body spacer. The method also includes forming an isolation layer on the substrate, wherein the isolation layer partially exposes the body spacer and thus defines a fin above the isolation layer. The method also includes forming a gate stack intersecting the fins on the isolation layer.