FinFET Fin Boundary Layout for Faster Mixed-Signal SerDes Circuits
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Solution Overview
Problem
Existing semiconductor structures face limitations in performance improvements as manufacturing processes are scaled down, as analog circuit design rules and boundaries restrict device size and performance parameters such as trans-conductance (GM), unit gain frequency (UGF), and electromigration (EM) currents, especially in high-speed circuits like serializer/deserializer (serdes) circuits.
Innovation Solution
Implementing a combination of analog and digital circuit design rules with different fin boundaries to design and manufacture circuits, allowing for higher trans-conductance (GM), unit gain frequency (UGF), and electromigration (EM) currents, by using digital fin boundaries that reduce device size and enable higher active area densities and routing space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional analog circuit design rules with analog fin boundary are used, then device performance can be maintained at current sizes, but device size cannot be reduced further and operating speed cannot be increased
Solution Approach 1:
The patent segments the fin boundary into two distinct types: analog fin boundary for analog circuits and digital fin boundary for digital circuits. This segmentation allows each boundary type to be optimized independently for its specific circuit type, enabling digital circuits to achieve higher operating speeds without being constrained by analog fin boundary limitations.
Solution Approach 2:
The patent applies different fin boundary characteristics to different locations in the semiconductor device. Digital finfet cells use digital fin boundary with specific properties optimized for digital operation, while analog finfet cells use analog fin boundary. This local differentiation resolves the contradiction by providing location-specific optimization.
2Area of moving object
If device size is reduced to achieve higher integration, then area is reduced, but performance improvements are limited by the analog fin boundary constraints
Solution Approach 1:
By segmenting the device into digital and analog regions with appropriate fin boundaries, the patent enables aggressive scaling of digital circuits to reduce area while maintaining performance reliability through the use of digital fin boundary optimized for high-speed operation.
Solution Approach 2:
The patent changes the fin boundary parameter from analog to digital type in digital finfet cells, which fundamentally alters the electrical characteristics and enables both area reduction and performance maintenance simultaneously.
3Reliability
If larger contact poly pitch and wider metal structures are used to improve GM, UGF, and EM currents, then these key device parameters are improved, but device size increases and scaling is limited
Solution Approach 1:
The patent changes the fin boundary parameter from analog to digital type, which fundamentally alters the electrical characteristics of the finfet cell. This parameter change enables improved GM, UGF, and EM currents without increasing device area, as the digital fin boundary provides optimized electrical properties for high-speed operation.
Solution Approach 2:
The digital fin boundary serves multiple functions: it provides optimized electrical characteristics for high GM and UGF, enables smaller device area, and supports higher operating speeds simultaneously, replacing the need for larger physical structures.
4Area of stationary object
If digital finfet cells are placed next to logic cells, then space usage is optimized and integration is improved, but traditional analog fin boundary requires keep-out zones that reduce space efficiency
Solution Approach 1:
The patent segments the fin boundary type based on circuit type, allowing digital finfet cells to use digital fin boundary that can be directly adjacent to logic cells without keep-out zones, while analog finfet cells use analog fin boundary. This segmentation enables direct placement and maximizes space usage efficiency.
Solution Approach 2:
By applying digital fin boundary locally to digital finfet cells, the patent enables direct placement next to logic cells in the same region, eliminating the need for keep-out zones and optimizing space usage in digital circuit areas.
Data Source
AI summary
A semiconductor structure including first finfet cells and second finfet cells. Each of the first finfet cells has an analog fin boundary according to analog circuit design rules, and each of the second finfet cells has a digital fin boundary according to digital circuit design rules. The semiconductor structure further includes first circuits formed with the first finfet cells, second circuits formed with the second finfet cells, and third circuits formed with one or more of the first finfet cells and one or more of the second finfet cells.