FinFET Buffer Layer Reduces Lattice Mismatch Defects
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Solution Overview
Problem
The performance of FinFETs using silicon as a channel layer is limited due to the high defect density caused by the significant lattice constant mismatch between group III-V materials and the silicon substrate, which affects the device's performance.
Innovation Solution
A FinFET fabrication method that involves forming trenches in a semiconductor substrate, depositing a buffer layer to fill and cover the substrate, and then etching to form a fin body with reduced defects, followed by the deposition of a channel layer with a lattice constant closer to the group III-V materials, reducing lattice mismatch and defect density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If group III-V materials layer is formed directly on the silicon substrate using epitaxy process, then carrier mobility is enhanced and driving current is increased, but defect density becomes significantly high due to lattice mismatch
Solution Approach 1:
A buffer layer is introduced as an intermediary between the silicon substrate and the group III-V channel layer. This buffer layer has a lattice constant that is intermediate between silicon and group III-V materials, serving as a transition layer that reduces the lattice mismatch. The buffer layer absorbs the lattice constant difference, enabling the formation of high-quality group III-V channel layers with reduced defect density while maintaining the carrier mobility enhancement benefits.
Solution Approach 2:
The lattice constant parameter is gradually changed through the buffer layer, which has a lattice constant intermediate between silicon and group III-V materials. This gradual parameter transition reduces the abrupt lattice mismatch, allowing for controlled epitaxial growth of the channel layer with significantly reduced dislocation and defect density, thereby improving device reliability.
2Length of moving object
If feature size of silicon-based device is decreased, then device scaling is achieved, but performance improvement is limited due to silicon material restrictions
Solution Approach 1:
The device structure is made composite by combining silicon substrate with group III-V materials for the channel layer. This composite structure leverages the mature silicon substrate technology for fabrication while utilizing the superior carrier mobility properties of group III-V materials in the active channel region, thereby achieving both scaling and performance improvement.
3Manufacturing precision
If buffer layer is formed to reduce lattice mismatch, then defect density is reduced, but device structure becomes more complex
Solution Approach 1:
The device structure is segmented into distinct functional layers: silicon substrate, buffer layer, and group III-V channel layer. Each layer serves a specific function - the substrate provides mechanical support and electrical connection, the buffer layer manages lattice mismatch, and the channel layer provides high-mobility conduction. This segmentation allows for optimized fabrication processes for each layer while maintaining overall device performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method significantly reduces defect density in the buffer and channel layers, enhancing the performance of the FinFET by improving carrier mobility and device reliability.
Implementation Method 1
the group III-V materials layer formed directly on the silicon substrate using an epitaxy process may have a significant high defect density
Data Source
AI summary
FinFET and fabrication method thereof. The FinFET fabrication method includes providing a semiconductor substrate; forming a plurality of trenches in the semiconductor substrate, forming a buffer layer on the semiconductor substrate by filling the trenches and covering the semiconductor substrate, and forming a fin body by etching the buffer layer. The FinFET fabrication method may further includes forming a insulation layer on the buffer layer around the fin body; forming a channel layer on the surface of the fin body; forming a gate structure across the fin body; forming source/drain regions in the channel layer on two sides of the gate structure; and forming an electrode layer on the source/drain regions.