FinFET Buffer Patterns for Leakage Reduction and Mobility
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Solution Overview
Problem
As feature sizes of semiconductor devices decrease, high leakage current due to short-channel effects deteriorate their reliability and performance, necessitating the development of methods to reduce short-channel effects and enhance carrier mobility, such as forming fin-type field effect transistors (FinFETs) and strained channels.
Innovation Solution
The semiconductor device incorporates fin-type field effect transistors with specific buffer and channel patterns made of semiconductor materials like germanium, where the lattice constants and germanium concentrations are strategically graded to create compressively-strained or strain-relaxed channel regions, and the use of epitaxial layers to optimize channel width and carrier mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes of semiconductor devices are decreased, then device integration and scaling are improved, but leakage current increases due to short-channel effects
Solution Approach 1:
The patent transitions from planar transistors to three-dimensional FinFET structures, utilizing vertical fins extending from the substrate to create additional current conduction paths while maintaining control over the channel, thereby reducing short-channel effects and leakage current at scaled dimensions
Solution Approach 2:
The patent modifies material parameters by introducing strained semiconductor layers with different lattice constants, altering the physical properties of the channel to reduce carrier mobility and suppress leakage current while maintaining device functionality at scaled feature sizes
2Reliability
If fin-type field effect transistors are formed, then short-channel effects are reduced, but device complexity increases
Solution Approach 1:
The patent divides the semiconductor structure into multiple discrete layers including buffer layers, strained channel layers, and cap layers, each with specific functions, allowing complex FinFET structures to be manufactured through sequential deposition processes
Solution Approach 2:
The patent introduces buffer layers with intermediate lattice constants between the substrate and the strained channel layer, acting as intermediaries that gradually transition the lattice mismatch and prevent dislocation propagation, thereby simplifying the overall manufacturing process
3Speed
If strained channels are formed, then carrier mobility is increased, but manufacturing precision requirements increase due to lattice mismatch management
Solution Approach 1:
The patent systematically varies the composition and thickness parameters of strained semiconductor layers, optimizing the lattice constant differences to induce controlled strain that enhances carrier mobility while remaining within manufacturing tolerances
Solution Approach 2:
The patent applies strain locally to specific channel regions by forming strained semiconductor layers only in the channel area, while maintaining relaxed buffer layers in other regions, thereby achieving high carrier mobility where needed without excessive manufacturing complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces leakage current and enhances carrier mobility, leading to improved reliability and performance of semiconductor devices by managing lattice mismatch and dislocation spreading, while also allowing for efficient strain induction in channel regions.
Implementation Method 1
the lattice constant the third buffer pattern may be less than that of the second channel pattern at an interface therebetween such that the second channel pattern defines a compressively-strained channel region of the second MOS transistor
Implementation Method 2
managing lattice mismatch and dislocation spreading
Implementation Method 3
The first and second channel patterns and the first, second and third buffer patterns may be epitaxial layers
Data Source
AI summary
A semiconductor device includes a substrate having a first region and a second region, a first MOS transistor including a first fin structure and a first gate electrode in the first region, the first fin structure having a first buffer pattern, a second buffer pattern, and a first channel pattern which are sequentially stacked on the substrate, and a second MOS transistor including a second fin structure and a second gate electrode in the second region, the second fin structure having a third buffer pattern and a second channel pattern which are sequentially stacked on the substrate. Related fabrication methods are also discussed.