FinFET Fabrication on Bulk Substrates via Dummy Fin Isolation
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Solution Overview
Problem
The fabrication of FinFET integrated circuits on bulk semiconductor substrates faces challenges due to etch pattern loading, which results in variance in fin width and trench depth, making reliable processing difficult, especially in the logic portion of the IC where variations cannot be compensated by design changes.
Innovation Solution
A method involving the formation of a patterned hard mask to define a regular array of fins, followed by etching and partial removal of dummy fins to create isolation regions, with insulating material deposition to fill trenches and cover removed fins, ensuring uniformity and electrical isolation between fins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If dummy fins are added to achieve a regular array for uniform etching, then etch pattern loading is reduced and fin uniformity is improved, but the complexity of removing dummy fins and achieving electrical isolation increases significantly on bulk semiconductor substrates
Solution Approach 1:
The method performs preliminary actions by forming dummy fins and trenches before the main fin formation process. The dummy fins are created as part of the initial patterning step, and their removal is planned and executed as an integrated part of the overall fin formation process, rather than as a separate corrective step. This preliminary structuring allows for uniform etching conditions to be established before the actual fin etching begins.
Solution Approach 2:
The fabrication process is segmented into distinct phases: first forming a complete regular array including dummy fins to establish uniform etching conditions, then selectively removing dummy fins in a controlled manner. The removal process itself is segmented by using specific etch conditions that remove dummy fins at different rates or at different stages than the main fins, allowing for systematic elimination of dummy structures while preserving functional fins.
2Manufacturing precision
If a regular array of fins is etched to minimize loading effects, then etch uniformity is improved, but the horizontal surface area required increases due to the need for dummy fins
Solution Approach 1:
The method applies partial action by forming dummy fins that extend beyond the actual device boundaries. These extra dummy fins are intentionally created to establish uniform etching conditions across the entire array, even though they will be removed later. The excessive action involves creating more fins than ultimately needed, with the understanding that the dummy portions will be eliminated in subsequent processing steps to recover the required layout density.
3Reliability
If dummy fins are removed to achieve electrical isolation, then proper fin isolation is achieved, but the processing difficulty and risk of damage to remaining fins increases on bulk substrates
Solution Approach 1:
The method applies local quality by creating regions with different properties: dummy fins are positioned in specific locations where removal is desired, while functional fins are positioned where they must be preserved. The etch process is localized to affect only the dummy fin regions through selective masking or etch condition control. This local differentiation allows dummy fins to be removed while leaving functional fins intact, achieving electrical isolation without compromising the remaining device structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes etch pattern loading, achieving uniform fin arrays and effective electrical isolation, reducing the risk of circuit failure by maintaining consistent device characteristics across the IC.
Implementation Method 1
Portions of the patterned hard mask are removed using a cut mask to form a modified hard mask
Implementation Method 2
The substrate is etched using the modified hard mask as an etch mask to form a plurality of fins extending upwardly from the substrate and separated by trenches
Implementation Method 3
an insulating material is deposited to fill the trenches and to cover the at least partially removed selected ones of the plurality of fins
Data Source
AI summary
Methods are provided for fabricating FinFET integrated circuits on bulk semiconductor substrates. In accordance with one embodiment a patterned hard mask that defines locations of a regular array of a plurality of fins is formed overlying a semiconductor substrate. Portions of the patterned hard mask are removed using a cut mask to form a modified hard mask. The substrate is etched using the modified hard mask as an etch mask to form a plurality of fins extending upwardly from the substrate and separated by trenches. Selected ones of the plurality of fins are at least partially removed to form isolation regions and an insulating material is deposited to fill the trenches and to cover the at least partially removed selected ones of the plurality of fins.