FinFET Bulk Epitaxial Layer for Sheet Resistance Reduction

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

As FinFETs shrink, the epitaxial layer serving as the source/drain region decreases, leading to a smaller contact area between the contact plug and the epitaxial layer, resulting in increased sheet resistance.

Innovation Solution

A method is developed to form a FinFET with a specific shape epitaxial layer where all fin structures share a bulk epitaxial layer at the same side of the gate structure, reducing the number of individual epitaxial layers and enhancing contact efficiency by creating a recessed and protruding profile on the substrate, allowing the epitaxial layer to contact the bottom of both first and second recesses directly.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the FinFET size is reduced to continue scaling, then the transistor density and integration capability are improved, but the epitaxial layer area shrinks leading to increased sheet resistance

Engineering Contradiction:
Improvetransistor densityVSAvoidsheet resistance
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

Multiple separate epitaxial layers that would normally be formed under each individual fin structure are merged into a single continuous bulk epitaxial layer by removing the STI between fins and forming a unified recessed profile. This merging increases the effective contact area for the contact plug while maintaining compatibility with scaled FinFET dimensions, thereby reducing sheet resistance without sacrificing transistor density.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The invention transitions from a planar epitaxial layer configuration to a three-dimensional bulk epitaxial layer that extends across multiple fin structures. By creating a bulk epitaxial layer with vertical extent and horizontal continuity, the contact area is increased in multiple dimensions, allowing the contact plug to establish better electrical connection even as the overall device size is reduced.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Ease of manufacture

If conventional separate epitaxial layers are used under each fin, then the manufacturing process is simpler, but the resistance is higher due to smaller contact area

Engineering Contradiction:
Improvemanufacturing process simplicityVSAvoidelectrical resistance
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The invention combines multiple discrete epitaxial layer formation steps into a single bulk epitaxial layer formation process. By removing the STI between fins and creating a unified recessed profile, the process merges what would otherwise be separate epitaxial growth regions into one continuous structure, reducing resistance while maintaining manufacturing feasibility through standardized semiconductor processing techniques.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The STI (shallow trench isolation) material is selectively removed from between the fin structures to enable the formation of a continuous bulk epitaxial layer. This extraction of the isolating material creates the necessary space for the epitaxial layer to span across multiple fins, increasing the contact area and reducing resistance without adding significant process complexity.

Inventive Principle:
Principle #2Taking out (Extraction)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration results in a bulk epitaxial layer with lower resistance compared to conventional epitaxial layers, improving the electrical connectivity and reducing sheet resistance.

Implementation Method 1

an epitaxial layer is formed on the first recessed and protruding profile

Methodology Applied
Scientific EffectEpitaxial growth: Epitaxy

Data Source

PatentUS9978873B2Method for fabricating FinFet
Publication Date: 2018.05.22 UNITED MICROELECTRONICS CORP
  • US9978873B2 patent drawing
  • US9978873B2 patent drawing
  • US9978873B2 patent drawing

AI summary

The present invention provides a method of fabricating a FinFET, comprising the following steps: first, a substrate having a plurality of fin structures disposed thereon is provided, an STI disposed between adjacent fin structures and a gate structure crossing the fin structures. Next, the fin structures not covered by the gate structure and the STI not covered by the gate structure are etched, until the STI is removed entirely and a first recessed and protruding profile is formed on the substrate, wherein the first recessed and protruding profile includes a first recess and a plurality of second recesses, and the position of the second recesses corresponds to the position of the fin structures, and an epitaxial layer is formed on the first recessed and protruding profile.