FinFET Fabrication Using Bulk Substrate Segmentation
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Solution Overview
Problem
The semiconductor industry faces challenges in producing high-quality FinFETs using conventional bulk wafers due to issues with device width and sub-threshold leakage control, and the use of Silicon-On-Insulator (SOI) wafers is expensive.
Innovation Solution
A method for making FinFETs using a bulk semiconductor substrate with a SiGe layer and a Si layer, where the lattice constant of the SiGe layer matches the substrate, forming a Fin structure, and epitaxially growing stressed source and drain regions to enhance carrier mobility and reduce parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional bulk wafers are used to make FinFETs, then production cost is reduced, but device width control and sub-threshold leakage control deteriorate
Solution Approach 1:
The bulk wafer is segmented into multiple functional layers: a first semiconductor layer forming the Fin structure, a second semiconductor layer forming source/drain regions, and an insulator layer. This segmentation allows precise control of device dimensions and electrical characteristics while maintaining compatibility with bulk wafer processing, resolving the contradiction between cost and manufacturing precision.
Solution Approach 2:
Different regions of the bulk wafer are given different properties: the first semiconductor layer is patterned to form fins with specific geometries, the insulator layer is positioned to control sub-threshold leakage locally, and the second semiconductor layer is doped to form source/drain regions. This local differentiation enables precise device width and leakage control without requiring expensive SOI wafers.
2Manufacturing precision
If SOI wafers are used to make FinFETs, then device width control and sub-threshold leakage control are improved, but production cost increases
Solution Approach 1:
The patent replaces expensive SOI wafers with conventional bulk wafers that can be processed using existing CMOS fabrication techniques. The insulator layer is introduced as a localized feature rather than requiring a complete SOI substrate, significantly reducing material costs while maintaining the necessary device control characteristics.
Solution Approach 2:
The invention changes the fundamental parameter of substrate type from SOI to bulk silicon, and introduces an insulator layer with specific thickness and positioning parameters to achieve the desired electrical characteristics. This parameter transformation allows achieving SOI-level performance with bulk wafer cost structure.
3Object-affected harmful factors
If the insulator layer is formed between gate and source/drain, then parasitic capacitance is reduced, but manufacturing complexity increases
Solution Approach 1:
The insulator layer formation is merged with the existing gate and source/drain fabrication processes. The same photolithography and etching steps used to define the gate also define the insulator layer boundaries, and the insulator deposition is integrated into the interlayer dielectric formation process. This merging reduces manufacturing complexity despite the added functional layer.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for FinFETs with improved control over device width and sub-threshold leakage, reduced Short Channel Effect, and lower production costs compared to SOI wafers, while enabling easy adjustment of device width and reduced source/drain resistance.
Implementation Method 1
a SiGe layer on the semiconductor substrate and a Si layer on the SiGe layer, wherein the lattice constant of the SiGe layer matches with that of the substrate
Implementation Method 2
epitaxially growing stressed source and drain regions located on both sides of the Fin structure and the insulator
Data Source
AI summary
A method for making FinFETs and semiconductor structures formed therefrom is disclosed, comprising: providing a SiGe layer on a Si semiconductor substrate and a Si layer on the SiGe layer, wherein the lattice constant of the SiGe layer matches that of the substrate; patterning the Si layer and the SiGe layer to form a Fin structure; forming a gate stack on top and both sides of the Fin structure and a spacer surrounding the gate stack; removing a portion of the Si layer which is outside the spacer with the spacer as a mask, while keeping a portion of the Si layer which is inside the spacer; removing a portion of the SiGe layer which is kept after the patterning, to form a void; forming an insulator in the void; and epitaxially growing stressed source and drain regions on both sides of the Fin structure and the insulator.