FinFET Buried Contact Structure for Lower Capacitance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor devices face challenges in improving device performance and reliability, particularly in reducing capacitance between contacts and ensuring electrical stability as pitch sizes decrease, while effectively managing the short channel effect in multi-gate transistors.
Innovation Solution
The semiconductor device design incorporates a substrate with fin-type patterns, source/drain patterns, and buried conductive patterns, featuring specific insulating liner thickness variations and curved portions to optimize electrical connections and reduce capacitance, enhancing performance and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the pitch size of semiconductor devices is decreased to increase density, then device density is improved, but capacitance between contacts increases and electrical stability deteriorates
Solution Approach 1:
The patent introduces a vertical dimension by forming a buried conductive pattern that extends from the first surface toward the second surface of the substrate, and a contact connection via that connects the source/drain contact to the buried conductive pattern. This three-dimensional configuration reduces the capacitance between contacts by separating them in the vertical direction while maintaining high device density through efficient space utilization.
Solution Approach 2:
The patent introduces an intermediate buried conductive pattern and contact connection via structure that mediates between the source/drain contact and the substrate. This intermediate structure reduces direct capacitance between contacts by providing an indirect connection path, thereby improving electrical stability while maintaining decreased pitch dimensions.
2Ease of operation
If multi-gate transistors are used to improve current control capability, then current control is improved, but short channel effect is exacerbated without proper suppression structures
Solution Approach 1:
The patent applies preliminary anti-action by forming a buried conductive pattern and contact connection via structure that preemptively suppresses the short channel effect before it can significantly impact device performance. The vertical extension of the buried conductive pattern creates an electric field that counteracts the potential well formation in the channel region, thereby suppressing carrier accumulation and reducing the short channel effect while maintaining the multi-gate transistor's current control capabilities.
3Ease of manufacture
If conventional contact structures are used with uniform insulating liner thickness, then manufacturing is simplified, but capacitance between contacts increases
Solution Approach 1:
The patent applies local quality by forming insulating liners with non-uniform thickness around the buried conductive pattern and contact connection via. The insulating liner thickness is varied locally to optimize the electrical characteristics, providing greater insulation where needed to reduce capacitance between contacts while maintaining manufacturability through controlled deposition processes.
Data Source
AI summary
A semiconductor device includes a substrate that has first and second surfaces opposite to each other in a first direction, a first fin-type pattern that protrudes in the first direction from the first surface of the substrate and extends in a second direction, a first source/drain pattern on the first fin-type pattern, a first source/drain contact on the first source/drain pattern, a contact connection via that extends in the first direction and is electrically connected to the first source/drain contact, a buried conductive pattern that is in the substrate, is electrically connected to the contact connection via, and has first and second surfaces opposite to each other in the first direction, the first surface of the buried conductive pattern facing the first source/drain contact, and first buried insulating liners that extend along sidewalls and along the first surface of the buried conductive pattern.