FinFET Substrate Isolation via Selective Oxidation
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Solution Overview
Problem
Conventional techniques for manufacturing nonplanar transistors, such as FinFETs, face challenges in forming compound semiconductor channels and insulating features due to lattice structure differences, leading to undesirable strains and defects, which hinder the advancement of IC design and performance.
Innovation Solution
A method involving the formation of a buried isolation layer using silicon germanium oxide to electrically isolate FinFETs from the substrate, reducing channel strain and enhancing device performance by using a selective oxidation process that selectively oxidizes silicon germanium without affecting the silicon substrate, and forming a gate stack that wraps around the channel region to improve control and reduce leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional techniques are used to form compound semiconductor channel on elementary semiconductor substrate, then manufacturing process is simple, but undesirable channel strains and lattice defects are produced
Solution Approach 1:
A buried isolation layer is introduced as an intermediary between the silicon substrate and the compound semiconductor channel. This isolation layer acts as a buffer that decouples the lattice mismatch between silicon and compound semiconductor, preventing strain and defect propagation while allowing the channel to maintain its desired crystal structure and electrical properties
Solution Approach 2:
The structure is segmented into distinct layers: silicon substrate, buried isolation layer, and compound semiconductor channel. This segmentation allows each layer to be optimized independently - the substrate provides mechanical support, the isolation layer provides lattice buffering, and the channel provides electrical function - thereby resolving the contradiction between manufacturing simplicity and structural integrity
2Ease of manufacture
If conventional techniques are used to form insulating feature between channel region and substrate, then manufacturing process is simple, but effective electrical isolation is not achieved
Solution Approach 1:
The buried isolation layer serves as an intermediary insulating structure that provides effective electrical isolation between the compound semiconductor channel and the silicon substrate. By positioning this isolation layer at the interface, it effectively blocks charge carrier leakage paths while maintaining compatibility with standard fabrication processes
Solution Approach 2:
Instead of forming insulating features in the lateral plane, the solution moves to the vertical dimension by introducing a buried isolation layer beneath the channel. This dimensional shift allows for more effective electrical isolation while avoiding the complexity of lateral isolation structure fabrication
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces the punch-through effect, enhances carrier mobility, and improves device performance by isolating the FinFETs from the substrate, resulting in increased speed and reduced leakage, while maintaining a smaller footprint.
Implementation Method 1
a selective oxidation process that selectively oxidizes silicon germanium without affecting the silicon substrate
Data Source
AI summary
Integrated circuit devices, such as fin-like field effect transistors, and methods of fabricating thereof are disclosed herein. An exemplary device includes a fin that includes a first semiconductor layer and a second semiconductor layer disposed on the first semiconductor layer. The second semiconductor layer includes a partially oxidized portion and a completely oxidized portion. A third semiconductor layer is disposed on the partially oxidized portion of the second semiconductor layer, where a source region and a drain region are defined in the third semiconductor layer. A fourth semiconductor layer is disposed on the completely oxidized portion of the second semiconductor layer, where a channel region is defined in the fourth semiconductor layer between the source region and the drain region defined in the third semiconductor layer. A gate structure is disposed over the channel region defined in the fourth semiconductor layer of the fin.