FinFET Device Structure With Heavily-Doped Buried Layer
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Solution Overview
Problem
FinFET devices face reliability concerns due to radiation effects, self-heating, and latchup issues, particularly in bulk CMOS and silicon on insulator (SOI) technologies, which affect their performance and longevity.
Innovation Solution
The implementation of a FinFET structure with a heavily-doped buried layer and vertical connecting implants to reduce thermal and electrical resistance, combined with a buried oxide layer, enhances the FinFET's reliability by improving heat transfer and radiation immunity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If FinFET structures are scaled down to maintain dimensional similitude, then device density increases, but reliability deteriorates due to radiation effects and self-heating
Solution Approach 1:
A heavily-doped buried layer is introduced as an intermediary structure between the FinFET channel and the substrate. This buried layer acts as a mediator that provides radiation hardening by capturing and neutralizing radiation-induced carriers, thereby protecting the channel region from total ionizing dose effects while maintaining scaled dimensions
Solution Approach 2:
The patent applies local quality by creating a heavily-doped region specifically in the buried layer beneath the FinFET channel, while keeping the channel itself lightly-doped to maintain mobility. This localized doping approach provides radiation hardness exactly where needed without compromising the electrical performance of the channel region
2Stability of the object's composition
If isolation regions are used to separate FinFET structures, then device isolation improves, but thermal resistance increases leading to self-heating
Solution Approach 1:
The heavily-doped buried layer serves as a thermal intermediary that provides a low-resistance thermal pathway between the FinFET channel and the substrate. This buried layer mediates heat transfer, conducting thermal energy away from the channel region through the isolation regions to the substrate, thereby reducing self-heating while maintaining device isolation
3Stability of the object's composition
If the fin body is separated from the substrate by isolation regions, then device isolation is achieved, but thermal transfer to the substrate is prevented
Solution Approach 1:
The patent creates a localized heavily-doped region in the buried layer directly beneath the fin body connecting region. This localized high-doping provides a thermal conduit that allows thermal energy to transfer efficiently from the fin body to the substrate through the isolation regions, while the surrounding lightly-doped isolation regions maintain electrical isolation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively reduces self-heating, enhances latchup immunity, and improves radiation resistance, leading to more reliable FinFET devices with increased circuit density and reduced sensitivity to transient events.
Implementation Method 1
The implementation of a FinFET structure with a heavily-doped buried layer and vertical connecting implants to reduce thermal and electrical resistance, combined with a buried oxide layer, enhances the FinFET's reliability by improving heat transfer
Implementation Method 2
Ionizing radiation occurs naturally in the form of high-energy photons or charged particles that possess enough energy to break atomic bonds and create electron hole pairs in an absorbing material
Implementation Method 3
as an ionizing particle passes through a FinFET device, it generates one or more electron-hole pairs which can be trapped in the gate oxides and the field oxides
Data Source
AI summary
A low electrical and thermal resistance FinFET device includes a semiconductor body, a fin body on the substrate wafer, an isolation structure forming a fin connecting region, a gate dielectric on the fin body extending above the isolation structure, a FinFET gate electrode on the gate dielectric, a heavily-doped buried layer in the semiconductor body extending under said fin, and a vertical conductive region extending from the semiconductor body surface to the heavily-doped buried layer. Additionally, a fin body-to-buried layer implanted region disposed in the fin connecting region provides a low electrical and thermal resistance shunt from the fin body to the heavily-doped buried layer.