FinFET With Buried Oxide Region In Source/Drain
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Solution Overview
Problem
Conventional planar FETs face challenges such as sub-threshold swing degradation, significant drain-induced barrier lowering, and fluctuation of device characteristics when reduced in size, necessitating the development of more efficient semiconductor devices.
Innovation Solution
The formation of FinFETs with semiconductor fins and the integration of buried oxide regions in the source/drain regions to apply compressive strain to the channel region, enhancing device performance and reducing leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If planar FETs are reduced in size to increase density, then productivity increases, but device reliability deteriorates due to sub-threshold swing degradation, drain-induced barrier lowering, and leakage
Solution Approach 1:
The patent transitions from planar FETs to FinFETs by introducing a vertical fin structure that extends above the substrate surface. This dimensional change increases the effective channel width and surface area for current flow without increasing the footprint area, thereby improving device density while maintaining reliable electrical characteristics through better gate control and reduced leakage
Solution Approach 2:
The patent introduces an oxide region specifically within the source/drain region of the FinFET, creating a localized modification that applies compressive strain to the channel. This local quality change improves carrier mobility and device performance without affecting the overall device structure or requiring complete redesign of the FET architecture
2Area of stationary object
If planar FETs are reduced in size, then area decreases, but harmful factors increase due to significant drain-induced barrier lowering and leakage
Solution Approach 1:
By forming vertical fins that extend above the substrate, the patent achieves higher effective channel width within a smaller footprint. The three-dimensional fin structure provides better gate control over the channel, reducing drain-induced barrier lowering effects while maintaining compact device dimensions
Solution Approach 2:
The oxide region is locally introduced in the source/drain area to apply compressive strain specifically to the channel region. This localized modification reduces leakage and improves carrier mobility without requiring changes to the overall device footprint or introducing additional harmful effects
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach improves the performance of FinFETs by reducing leakage and enhancing device characteristics, addressing the limitations of planar FETs, particularly in densely packed semiconductor processing environments.
Implementation Method 1
the integration of buried oxide regions in the source/drain regions to apply compressive strain to the channel region
Data Source
AI summary
Embodiments of the present disclosure include a semiconductor device, a FinFET device, and methods for forming the same. An embodiment is a semiconductor device including a first semiconductor fin extending above a substrate, the first semiconductor fin having a first lattice constant, an isolation region surrounding the first semiconductor fin, and a first source/drain region in the first semiconductor fin, the first source/drain having a second lattice constant different from the first lattice constant. The semiconductor device further includes a first oxide region along a bottom surface of the first source/drain region, the first oxide region extending into the isolation region.