FinFET Power Delivery Structure With Buried Substrate Interconnect
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Solution Overview
Problem
Semiconductor devices face challenges in effectively arranging power delivery structures within limited spaces, particularly in connecting metal lines of the back end of line (BEOL) to active regions across a semiconductor substrate.
Innovation Solution
The semiconductor device incorporates fin-type active patterns with varying widths, device isolation patterns, gate structures, source/drain regions, contact structures, a buried conductive structure, and a conductive through-structure to efficiently deliver power across the substrate, utilizing a buried conductive structure that replaces a portion of the gate isolation structure to enhance power delivery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a conductive through-structure is formed to penetrate the semiconductor substrate to connect power lines, then power delivery capability is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent transitions from planar power delivery to three-dimensional power delivery by forming conductive through-structures that penetrate the substrate thickness direction. This vertical dimension enables direct connection between upper and lower surface power lines, significantly improving power delivery capability while maintaining a compact footprint.
Solution Approach 2:
The conductive through-structures are integrated within the existing device architecture, nesting the power delivery function within the substrate structure itself. The through-structures are positioned to pass through isolation regions without disrupting active device areas, embedding the power delivery function seamlessly into the device layout.
2Productivity
If fin-type active patterns with varying widths are used, then power distribution efficiency is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies different fin widths at different locations to optimize power distribution. First fin-type active patterns have a first width while second fin-type active patterns have a second width different from the first, allowing tailored power delivery characteristics in different regions of the device based on local power requirements.
Solution Approach 2:
The device structure intentionally introduces asymmetry through varying fin widths. The first and second fin-type active patterns are deliberately made asymmetric in dimension, creating different electrical characteristics in different regions to optimize overall power distribution efficiency across the device.
Data Source
AI summary
An embodiment of the present inventive step provides a semiconductor device, comprising: first and second fin-type active patterns disposed on an upper surface of a substrate, and having different widths; first and second gate structures crossing the first and second fin-type active patterns, respectively; first and second source/drain regions disposed on the first and second fin-type active patterns, respectively; first and second contact structures connected to the first and second source/drain regions, respectively; a gate isolation structure adjacent to the first fin-type active pattern having a relatively large width; a buried conductive structure contacting one end surface of the gate isolation structure, and connected to the second contact structure; a conductive through-structure extending from a lower surface of the substrate, and connected to the buried conductive structure; and a first wiring layer electrically connected to the first contact structure and the buried conductive structure.