FinFET Fin Structure With Buried Source/Drains for Higher Array Density
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Solution Overview
Problem
As the number of memory cells in stacked memory arrays increases, the number of pass transistors required also increases, leading to a larger memory device size due to the need for more transistors under the memory array, which poses a challenge in accommodating the growing number of local access lines.
Innovation Solution
The solution involves positioning the source/drains of finFETs below the uppermost surface of the semiconductor fin, allowing for a reduced distance between them, which enables more transistors to be packed in the x-direction under a stacked memory array, thereby accommodating more memory cells without increasing the device size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of memory cells in stacked memory arrays is increased, then the storage capacity is improved, but the number of pass transistors required increases leading to larger device size
Solution Approach 1:
The source/drain structures are positioned in the vertical dimension below the uppermost surface of the semiconductor fin, rather than only in the horizontal plane. This vertical positioning allows for reduced horizontal distance between source and drain, enabling higher transistor density under the memory array without increasing device footprint.
2Adaptability or versatility
If more pass transistors are located under the memory array, then more local access lines can be accommodated, but the area required for transistor placement increases
Solution Approach 1:
By utilizing the vertical space below the uppermost surface of the semiconductor fin for source/drain positioning, the invention enables more transistors to be packed into the same horizontal area under the memory array, thereby accommodating more local access lines without expanding the device footprint.
Solution Approach 2:
The invention changes the spatial parameter of source/drain positioning from conventional horizontal alignment to vertical alignment below the fin surface. This parameter change reduces the horizontal distance between source and drain, increasing transistor density and enabling more access lines to be supported within the same area.
Data Source
AI summary
Methods of forming a transistor might include removing portions of a semiconductor to define a semiconductor fin having an upper portion having an uppermost surface at a first level and extending from the first level to a second level, and a lower portion, wider than the upper portion, having an uppermost surface at the second level and extending from the second level to a third level; forming first and second isolation regions at the third level and adjacent the lower portion of the semiconductor fin; forming a first dielectric overlying portions of the semiconductor that are lower than a level between the first level and the second level; forming a second dielectric overlying an exposed portion of the upper portion of the semiconductor fin; forming a conductor overlying the second dielectric; and forming first and second source/drains in the lower portion of the semiconductor fin at the second level.