FinFET Epitaxial Cap Layer Layout for Surface Evenness
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Solution Overview
Problem
Existing methods for fabricating semiconductor devices face challenges in achieving an even surface for epitaxial layers in non-planar metal-oxide semiconductor (MOS) transistors, such as fin field effect transistors (FinFETs), which affects device performance.
Innovation Solution
A method involving the formation of a gate structure on a substrate, followed by the growth of an epitaxial layer and a first cap layer with a V-shape profile and planar surfaces, is employed to improve surface uniformity and device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If selective epitaxial growth (SEG) technique is used to form epitaxial structure, then carrier mobility is increased through stress application, but the surface evenness of the epitaxial layer deteriorates in non-planar MOS transistors
Solution Approach 1:
The cap layer is divided into multiple segments with different thicknesses: a first cap layer portion with greater thickness and a second cap layer portion with lesser thickness. This segmentation allows different regions to serve different functions - the thicker portion provides stress induction while the thinner portion enables planarization, thus resolving the contradiction between maintaining carrier mobility and achieving surface evenness
Solution Approach 2:
Different regions of the cap layer are given different local properties - the first cap layer portion has greater thickness for stress induction, while the second cap layer portion has lesser thickness for planarization. This local differentiation allows the same structure to simultaneously satisfy both requirements of stress application and surface evenness in different spatial locations
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed method enhances the surface evenness of epitaxial layers, thereby improving the performance and reducing defects in semiconductor devices, particularly in non-planar MOS transistors.
Implementation Method 1
selective epitaxial growth (SEG) technique to form epitaxial structure such as silicon germanium (SiGe) epitaxial layer
Implementation Method 2
forming a first cap layer on the epitaxial layer
Data Source
AI summary
A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming an epitaxial layer adjacent to the gate structure, and then forming a first cap layer on the epitaxial layer. Preferably, a top surface of the first cap layer includes a curve concave upward and a bottom surface of the first cap layer includes a planar surface higher than a top surface of the substrate.