FinFET Source/Drain Epitaxial Size Monitoring via Capacitance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current methods for characterizing epitaxial growth in FinFET source/drain regions require destructive testing, which is inefficient and unreliable, especially due to the complex geometry of fin structures making it difficult to control and monitor epitaxial size effectively.
Innovation Solution
The implementation of interdigitated source/drain regions with capacitance measurements between adjacent epitaxially grown semiconductor material, allowing for non-destructive determination of epitaxial size by correlating capacitance values with epitaxial growth characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If destructive testing is used to characterize epitaxial growth, then measurement reliability is improved, but productivity is worsened due to loss of samples and time-consuming analysis
Solution Approach 1:
The patent replaces destructive physical analysis with electrical capacitance measurements. By measuring capacitance between interdigitated source and drain regions, the epitaxial size can be determined non-destructively, eliminating the need for sample destruction while maintaining measurement reliability
Solution Approach 2:
The patent creates an electrical model (capacitance measurement) that serves as a proxy for direct physical measurement. The capacitance value correlates to epitaxial size, allowing indirect but reliable measurement without destroying the sample
2Measurement precision
If physical analysis is used to track epitaxial growth, then measurement precision is improved, but device complexity is worsened due to additional processing steps
Solution Approach 1:
The interdigitated source and drain regions serve dual purposes: they function as active device components and simultaneously serve as capacitance sensors for epitaxial size measurement. This eliminates the need for separate monitor structures or additional processing steps
Solution Approach 2:
The device structure itself provides the measurement capability. The interdigitated source and drain regions automatically form a capacitance structure that can be measured to determine epitaxial size, requiring no external monitoring infrastructure
3Ease of manufacture
If SIMS pad monitor is used in planar fabrication, then ease of manufacture is improved, but measurement precision is worsened due to poor correlation with actual epitaxial size
Solution Approach 1:
The patent introduces capacitance measurement as an intermediary that directly correlates to epitaxial size. Unlike SIMS pad which measures composition, capacitance measurement directly reflects the physical dimensions of the epitaxial region through electrical field interactions
Solution Approach 2:
The patent changes the measurement parameter from compositional analysis (SIMS) to electrical property measurement (capacitance). This parameter change enables direct correlation with epitaxial size while maintaining ease of manufacture through standard electrical measurement techniques
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables accurate and non-destructive monitoring of epitaxial size, improving process control and yield optimization without the need for destructive testing, by measuring capacitance between interdigitated source and drain regions.
Implementation Method 1
measuring capacitance between adjacent interdigitated source and drain regions comprising epitaxially grown semiconductor material
Data Source
AI summary
A source/drain epitaxial electrical monitor and methods of characterizing epitaxial growth through capacitance measurements are provided. The structure includes a plurality of fin structures; one or more gate structures, perpendicular to and intersecting the plurality of fin structures. The structure further includes a first connection by a first contact at one fin-end of every other fin structure of the plurality of fin structures, and a second connection by a second contact at one end of an alternate fin structure of the plurality of fin structures.