FinFET Capacitor Layout for Higher On-Chip Density
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Solution Overview
Problem
Conventional methods for forming capacitors on IC chips result in low capacitor density per unit area, leading to suboptimal device performance due to excessive chip area usage.
Innovation Solution
The use of FinFET devices with high-k metal gate structures and cut-metal-gate (CMG) and cut-slot-contact (CSC) isolation structures allows for the formation of densely packed capacitors by etching trenches and filling them with dielectric materials, enabling capacitors to be formed in both the X-direction and Y-direction, thereby increasing density and optimizing chip area usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional methods are used to form capacitors on IC chip, then the fabrication process is simple, but the capacitor density per unit area is low
Solution Approach 1:
The patent implements capacitors in both the X-direction and Y-direction by forming first capacitors between gate structures extending in the first direction, and second capacitors between gate structures extending in the second direction. This two-dimensional capacitor arrangement dramatically increases capacitor density per unit area compared to conventional single-direction capacitor formation, while utilizing the same fabrication process steps for both directions.
2Area of stationary object
If conventional capacitor formation methods are used, then the fabrication process is straightforward, but excessive chip area is required
Solution Approach 1:
The gate structures serve dual functions: they act as functional transistor gates for device operation, and simultaneously serve as capacitor electrodes for energy storage. This multi-functionality eliminates the need for separate dedicated capacitor structures, thereby reducing overall chip area while maintaining high capacitor density through the interleaved arrangement of capacitors in both X and Y directions.
3Quantity of substance
If capacitors are densely packed using the proposed method, then capacitor density per unit area increases, but manufacturing precision requirements increase
Solution Approach 1:
The patent performs preliminary patterning and trench formation steps before capacitor dielectric filling, establishing precise alignment and dimensional control early in the fabrication process. The trenches are formed with controlled dimensions and positions using standard photolithography and etching techniques, ensuring that subsequent dielectric filling and electrode formation can be precisely positioned to achieve the desired capacitor density without requiring excessive manufacturing precision at later stages.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances capacitor density per unit area, provides better uniformity control, and is compatible with existing FinFET fabrication processes, resulting in improved device performance and scalability.
Implementation Method 1
a first gate structure and a second gate structure each extending in a first direction; a first conductive contact and a second conductive contact each extending in the first direction
Implementation Method 2
filling them with dielectric materials, enabling capacitors to be formed in both the X-direction and Y-direction
Data Source
AI summary
A first and a second gate structure each extend in a first direction. A first and a second conductive contact extend in the first direction and are separated from the first and second gate structures in a second direction. A first isolation structure extends in the second direction and separates the first gate structure from the second gate structure. A second isolation structure extends in the second direction and separates the first conductive contact from the second conductive contact. The first gate structure is electrically coupled to a first electrical node. The second gate structure is electrically coupled to a second electrical node different from the first electrical node. The first conductive contact is electrically coupled to the second electrical node. The second conductive contact is electrically coupled to the first electrical node.