FinFET Capacitor Gate Layout to Prevent Fin Tapering
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The scaling of semiconductor devices to FinFET technology faces challenges in maintaining electrical performance and process yield due to the consumption of fins during oxide layer growth, leading to reduced reliability and limited region utilization for transistors when heavily doped regions are formed.
Innovation Solution
A semiconductor device design incorporating a substrate with first and second regions, where a fin with a heavily doped region is formed, and a single diffusion break structure is introduced in the second region to support a capacitor gate structure, allowing for high integration and performance without reducing the area for gate structures, and mitigating tapering issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a heavily doped region is formed in fins to achieve high conductivity, then electrical performance is improved, but the fin consumes too much during oxide layer growth causing top tapering and reduced reliability
Solution Approach 1:
The substrate is divided into first regions (for transistors) and second regions (for capacitors), allowing the heavily doped region to be localized in the second region where it is needed for capacitor conductivity without affecting the fin structure in the first region where transistor performance is critical
Solution Approach 2:
The heavily doped region is formed only in the fin portion located in the second region, creating local high conductivity where the capacitor requires it, while leaving the fin portion in the first region undoped or lightly doped to maintain proper shape and transistor functionality
2Productivity
If a metal-oxide-semiconductor capacitor is formed in the FinFET structure, then integration density is improved, but the area for transistor formation is reduced
Solution Approach 1:
The substrate is segmented into first regions dedicated to transistor formation and second regions dedicated to capacitor formation, allowing both components to coexist without competing for the same space, thereby maintaining high integration density while preserving sufficient area for transistor structures
Solution Approach 2:
The capacitor structure utilizes the second region in a spatial arrangement that does not encroach on the first region area, effectively using available substrate space in different zones to accommodate both transistor and capacitor functions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design achieves high integration, high density, and high performance with improved reliability by utilizing the second region effectively and minimizing tapering of fins, thus enhancing the overall semiconductor device's structural integrity.
Implementation Method 1
the fin located in the second region includes a heavily doped region
Implementation Method 2
when an oxide layer is subsequently grown on the fins by performing a thermal oxidation process, the fins including the heavily doped regions would consume too much during the growth of the oxide layer
Data Source
AI summary
A semiconductor device including a substrate, a fin, a gate structure, a single diffusion break (SDB) structure and a capacitor gate structure. The substrate has a first region and a second region, wherein the second region is located between the adjacent first regions. The fin is disposed on the substrate, wherein the fin located in the second region includes a heavily doped region. The gate structure is disposed on the fin and located in the first region. The SDB structure is disposed on the fin and located in the second region. The capacitor gate structure is disposed on the fin and is located in the second region, wherein the capacitor gate structure is disposed on the SDB structure. A manufacturing method of a semiconductor device is also provided.