FinFET Capacitor Structure for Integrated Circuit Decoupling
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Solution Overview
Problem
Current capacitor structures in integrated circuits face challenges in achieving sufficient capacitance as technology scales down, leading to increased parasitic capacitance that slows down transistor switching and increases internal dynamic power, making it difficult to reduce dynamic IR drop effectively.
Innovation Solution
A FinFet capacitor structure is created using interleaved first via and metal layers connected to VDD or VSS power supply rails, forming non-parasitic capacitors that function as decoupling capacitors between VDD and VSS power supply rails, allowing for increased capacitance while fitting within a standard cell footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional fringe and gate capacitors are used, then the capacitor structure fits in a standard cell footprint, but the capacitance value is insufficient as technology scales down
Solution Approach 1:
The patent transitions from planar 2D capacitor structures to three-dimensional FinFET-based capacitor structures. The FinFET fins extend vertically from the substrate, creating vertical capacitance pathways between VDD and VSS that leverage the third dimension (height) to increase capacitance without expanding the horizontal footprint, thereby resolving the contradiction between achieving higher capacitance and maintaining compact structure.
Solution Approach 2:
The capacitor structure is nested within the standard FinFET cell footprint by utilizing the existing FinFET fin structures. The interleaved arrangement of VDD-connected and VSS-connected fins allows the capacitor to be embedded within the same spatial envelope as the transistor fins, effectively nesting the capacitor function within the transistor structure without requiring additional area.
2Quantity of substance
If capacitor size is increased to achieve sufficient capacitance, then capacitance value improves, but parasitic capacitance increases which slows down transistor switching
Solution Approach 1:
The capacitor is segmented into multiple discrete FinFET fins that are interleaved between VDD and VSS power rails. Instead of using a single large capacitor structure that would generate high parasitic capacitance, the total capacitance is distributed across multiple smaller fin segments. This segmentation reduces the parasitic capacitance associated with each individual capacitor element while maintaining the total desired capacitance value.
Solution Approach 2:
The patent applies different electrical connections to different spatial locations within the FinFET structure. Specifically, alternating fins are connected to VDD while adjacent fins are connected to VSS, creating localized capacitor elements with controlled parasitic characteristics. This local differentiation of electrical properties allows optimization of capacitance while minimizing harmful parasitic effects in each local region.
3Quantity of substance
If more capacitor structures are added to increase decoupling capacitance, then dynamic IR drop reduction improves, but routing layers are obstructed
Solution Approach 1:
The patent utilizes the vertical dimension by extending FinFET fins upward from the substrate to create capacitance. This vertical development allows the capacitor to achieve high capacitance values without occupying additional horizontal area that would be needed for traditional planar capacitor structures, thereby preserving routing layer area while increasing decoupling capacitance.
Solution Approach 2:
The FinFET fin structures serve dual functions: they act as both the active transistor channels and the capacitor electrodes. The same vertical fin structures that provide transistor functionality also provide the capacitor plates for decoupling capacitance, eliminating the need for separate dedicated capacitor structures that would obstruct routing layers.
Data Source
AI summary
A FinFet capacitor structure includes a first, second, third, and fourth FinFet fin, a contiguous gate layer over the fins, first and second source/drain contacts in direct physical contact with the first FinFet fin on either side of the gate layer, a first gate contact in direct physical contact with a portion of the contiguous gate layer directly over the second FinFet fin, third and fourth source/drain contacts in direct physical contact with the third FinFet fin on either side of the gate layer, and a second gate contact in direct physical contact with a portion of the contiguous gate layer directly over the fourth FinFet fin. The first, second, third, and fourth source/drain contacts are all connected to a first power supply rail, and the first and second gate contacts are all connected to a second power supply rail.