FinFET Capping Layer Reduces Punch-Through Leakage
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Solution Overview
Problem
FinFET devices suffer from punch-through leakage due to current leakage through the ungated portion of the fin, leading to increased static power consumption, and existing solutions like punch-through-stopper dopant implantation cause variability and mobility degradation.
Innovation Solution
A capping layer and isolation fill structure is formed over the fin, with the capping layer providing an interface dipole layer barrier to reduce punch-through leakage by creating increased negative or positive charges adjacent to the fin, reducing leakage without affecting carrier mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If punch-through-stopper dopant implantation is used to control punch-through leakage, then punch-through leakage is reduced, but carrier mobility deteriorates and variability increases due to random dopant fluctuation
Solution Approach 1:
A capping layer is introduced as an intermediary structure between the fin and the environment. This capping layer forms an interface dipole that creates an electric field to suppress punch-through leakage without requiring dopant implantation, thereby avoiding mobility degradation and RDF variability
Solution Approach 2:
The electrical field effect created by the capping layer interface dipole replaces the mechanical/chemical dopant implantation approach. Instead of using physical dopant atoms to control the electric field, the patent uses the electromagnetic field effect from the capping layer to achieve the same leakage suppression without the harmful side effects
2Object-affected harmful factors
If punch-through-stopper dopant implantation is used to control punch-through leakage, then punch-through leakage is reduced, but manufacturing precision deteriorates due to random dopant fluctuation
Solution Approach 1:
The capping layer serves as a mediator that provides deterministic control over the electric field at the fin interface. Unlike stochastic dopant placement, the capping layer's position and properties can be precisely controlled during deposition, eliminating random dopant fluctuation and improving manufacturing precision
Solution Approach 2:
The patent changes the approach from controlling dopant concentration and position (which are subject to statistical variation) to controlling the capping layer's physical and electrical parameters (thickness, material composition, interface quality) which can be more precisely controlled and reproduced in manufacturing
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The capping layer and isolation fill structure effectively reduces punch-through leakage in FinFETs by forming a barrier at the interface, addressing the limitations of existing methods that increase variability and degrade mobility.
Implementation Method 1
The capping layer and a lower portion of the fin define an interface dipole layer barrier, a portion of the capping layer operable to provide an increased negative charge or an increased positive charge adjacent to the fin, to reduce punch-through leakage
Data Source
AI summary
A method for forming FinFETs having a capping layer for reducing punch through leakage includes providing an intermediate semiconductor structure having a semiconductor substrate and a fin disposed on the semiconductor substrate. A capping layer is disposed over the fin, and an isolation fill is disposed over the capping layer. A portion of the isolation fill and the capping layer is removed to expose an upper surface portion of the fin. Tapping layer and a lower portion of the fin define an interface dipole layer barrier, a portion of the capping layer operable to provide an increased negative charge or an increased positive charge adjacent to the fin, to reduce punch-through leakage compared to a fin without the capping layer.