FinFET Capping Layer Oxygen Diffusion Barrier
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Solution Overview
Problem
Existing semiconductor devices face challenges in scaling down multigate transistors without compromising performance, particularly in controlling current and suppressing short channel effects.
Innovation Solution
The semiconductor device design includes a fin-type pattern with a metal gate electrode and a capping layer, where the capping layer is made of silicon nitride and the interlayer insulating layers have different materials, allowing for effective current control and suppression of short channel effects by maintaining the threshold voltage and preventing oxygen diffusion into the gate electrode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the device is scaled down to improve integration density, then productivity increases, but short channel effects worsen and current control capability deteriorates
Solution Approach 1:
The patent transitions from planar transistors to three-dimensional FinFET structures, where the channel forms a fin extending vertically from the substrate. This dimensional change increases the effective channel area without increasing the planar footprint, improving integration density while maintaining current control through the vertical fin geometry that provides better gate control over the channel.
Solution Approach 2:
The channel region is segmented into multiple fins rather than a single planar channel. This segmentation allows the gate to control current through multiple vertical channels simultaneously, improving current control capability and suppressing short channel effects while maintaining compact device footprint for high integration density.
2Reliability
If the gate length is increased to improve current control capability, then reliability improves, but the device area increases reducing productivity
Solution Approach 1:
Instead of increasing gate length in the planar direction, the patent extends the channel vertically to form fins. The gate wraps around the fin structure, providing enhanced control over the channel current without increasing the planar device area. The effective channel length is maintained while the vertical dimension provides additional control leverage.
Solution Approach 2:
The gate structure wraps around and encloses the fin channel, with the gate electrode positioned on sidewalls and top surface of the fin. This nested configuration maximizes gate control over the channel current while minimizing the planar footprint, achieving good current control without increasing device area.
3Device complexity
If a simple gate structure is used to reduce device complexity, then ease of manufacture improves, but current control capability deteriorates
Solution Approach 1:
The gate structure is designed to wrap around the fin channel, with gate electrodes positioned on the sidewalls and top surface of the fin. This nested configuration provides superior current control by maximizing gate-channel interface area while maintaining a relatively straightforward fabrication process using standard deposition and etching techniques.
Solution Approach 2:
The gate control is extended into the vertical dimension by wrapping around the fin structure, providing enhanced current control capability. Despite the three-dimensional geometry, the fabrication process uses conventional semiconductor manufacturing steps, keeping device complexity manageable while achieving improved reliability.
4Reliability
If the capping layer is made of silicon nitride to prevent oxygen diffusion, then reliability improves, but manufacturing precision requirements increase due to material compatibility constraints
Solution Approach 1:
The silicon nitride capping layer serves as an intermediary barrier between the metal gate electrode and the environment. It prevents oxygen diffusion into the gate electrode that would cause threshold voltage drift, while being compatible with standard semiconductor fabrication processes. The capping layer is deposited using conventional chemical vapor deposition techniques with controlled thickness to provide adequate protection without creating processing conflicts.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enables efficient current control and suppression of short channel effects, maintaining the threshold voltage and enhancing the performance of multigate transistors while scaling down the device.
Implementation Method 1
A capping layer covers the upper surface of the first interlayer insulating layer and the upper surface of the first gate electrode... preventing oxygen diffusion into the gate electrode
Data Source
AI summary
A semiconductor device is provided. The semiconductor device includes a first fin-type pattern on a substrate, a first interlayer insulating layer on the substrate, covering the first fin-type pattern and including a first trench, the first trench intersecting the first fin-type pattern, a first gate electrode on the first fin-type pattern, filling the first trench, an upper surface of the first gate electrode being coplanar with an upper surface of the first interlayer insulating layer, a capping layer extending along the upper surface of the first interlayer insulating layer and along the upper surface of the first gate electrode, and a second interlayer insulating layer on the capping layer, the second interlayer insulating layer including a material different from that of the capping layer.