FinFET Standard Cell Architecture for Diffusion Region Sharing
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Solution Overview
Problem
Conventional standard cell designs struggle to integrate logic cells with different fin counts, leading to diffusion breaks and adverse LOD effects, which hinder the sharing of diffusion regions and result in suboptimal performance and power characteristics.
Innovation Solution
The design of standard cell architectures that support multiple diffusion regions with finfets of the same or different fin counts, allowing easy abutment and diffusion fills between like fin counts, along with distributed power rail networks and selective control of threshold voltages, enables the integration of logic cells with different fin counts while mitigating LOD effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If logic cells with different fin counts are integrated using conventional techniques, then device functionality is achieved, but diffusion breaks occur causing adverse LOD effects and suboptimal performance
Solution Approach 1:
The standard cell architecture is segmented into multiple diffusion regions (first diffusion region and second diffusion region) with different fin counts, allowing each region to be independently optimized while maintaining overall cell functionality. This segmentation enables integration of cells with different fin counts without requiring uniform diffusion structures throughout the entire cell.
Solution Approach 2:
Different diffusion regions within the same standard cell are assigned different local qualities (different fin counts), where the first diffusion region has a first fin count and the second diffusion region has a second fin count. This local quality differentiation allows each region to be optimized for its specific function while avoiding diffusion breaks at cell boundaries.
2Reliability
If diffusion regions are extended to mitigate LOD effects, then transistor performance improves, but cell placement flexibility is hindered
Solution Approach 1:
The diffusion structure is segmented into multiple regions with different fin counts within the same standard cell, allowing performance optimization in specific regions without requiring uniform extension of diffusion across the entire cell. This maintains placement flexibility while achieving LOD mitigation where needed.
Solution Approach 2:
The fin count parameter is varied across different diffusion regions within the same standard cell, allowing optimization of LOD effects in specific regions without changing the overall cell dimensions or placement requirements. This enables performance tuning without sacrificing placement flexibility.
3Ease of manufacture
If logic cells are designed with uniform diffusion widths for abutment, then placement is simplified, but integration of cells with different fin counts becomes difficult
Solution Approach 1:
The standard cell is divided into multiple diffusion regions, each with its own fin count, while maintaining uniform overall cell width for abutment. This segmentation allows different fin counts to coexist within a uniform cell footprint, enabling both easy placement and versatile integration.
Solution Approach 2:
The standard cell architecture is designed to be universal by accommodating multiple diffusion regions with different fin counts within a single cell type. This multi-functionality allows the same cell width to support various fin count configurations, enabling both uniform abutment and flexible integration of different cell types.
Data Source
AI summary
Disclosed systems and methods pertain to finfet based integrated circuits designed with logic cell architectures which support multiple diffusion regions for n-type and p-type diffusions. Different diffusion regions of each logic cell can have different widths or fin counts. Abutting two logic cells is enabled based on like fin counts for corresponding p-diffusion regions and n-diffusion regions of the two logic cells. Diffusion fills are used at common edges between the two logic cells for extending lengths of diffusion, based on the like fin counts. The logic cell architectures support via redundancy and the ability to selectively control threshold voltages of different logic cells with implant tailoring. Half-row height cells can be interleaved with standard full-row height cells.