Fin-FET Cell Design Using Hierarchical Grid Alignment
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Solution Overview
Problem
Existing Electronic Design Automation (EDA) software tools fail to adequately address the additional constraints required for designing Fin-FET technology, necessitating considerable customization at various steps, which is inefficient and resource-intensive.
Innovation Solution
A computer-implemented method for designing circuits using Fin-FET technology, where cells are formed with specific boundary and shape configurations aligned to integer multiples of a pitch, allowing for hierarchical representation and reduced data complexity, thereby automating the design process without extensive customization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Fin-FET technology is used to reduce off-state leakage currents, then device reliability is improved, but design complexity increases due to additional constraints
Solution Approach 1:
The patent applies parameter changes by modifying the geometric parameters of Fin-FET structures (fin width, fin spacing, gate length) to optimize device performance. The methodology systematically varies these parameters to achieve desired electrical characteristics while managing design complexity through automated exploration of parameter spaces.
Solution Approach 2:
The patent segments the complex Fin-FET design process into distinct stages: parameter definition, constraint specification, automated layout generation, and verification. This segmentation allows each aspect to be handled separately by specialized software modules, reducing overall design complexity while maintaining reliability improvements.
2Ease of manufacture
If hierarchical layout representation is used to reduce data complexity, then ease of manufacture is improved, but design precision may be compromised
Solution Approach 1:
The patent implements hierarchical layout representation using a nested structure where standard Fin-FET cell templates contain embedded geometric patterns. These templates are recursively instantiated across the chip layout, with each hierarchy level managing specific aspects of the design. This nesting reduces data complexity by avoiding redundant shape definitions while preserving manufacturing precision through parameterized template instantiation.
Solution Approach 2:
The patent uses copying by creating reusable Fin-FET cell templates that can be instantiated multiple times throughout the layout. Instead of defining complete geometry for each transistor instance, the methodology copies and places template references with modified parameters, significantly reducing data complexity while maintaining exact geometric fidelity for manufacturing.
3Productivity
If automated EDA tools are used to streamline the design process, then productivity is improved, but adaptability to Fin-FET constraints decreases without customization
Solution Approach 1:
The patent enhances EDA tool adaptability by implementing a universal Fin-FET constraint module that can be integrated into existing automated design flows. This module provides multi-functional capabilities: it automatically generates Fin-FET-specific constraints, validates layouts against Fin-FET design rules, and optimizes placement and routing. The universal nature of this module allows it to work across different design stages and toolchains without requiring extensive customization, thereby maintaining both productivity and adaptability.
Data Source
AI summary
A computer implemented method for designing a circuit is presented. The method includes forming, using the computer, a multitude of cells. Each cell is characterized by a multitude of first shapes extending along a first direction. Each first shape is spaced, along a second direction substantially orthogonal to the first direction, from a neighboring first shape in accordance with a first pitch. Each cell is further characterized by a cell origin including a first cell coordinate associated with the second direction. The first cell coordinate is assigned in accordance with an integer multiple of the first pitch when the computer is invoked to form the multitude of cells representing the circuit.