FinFET Cell Layout With Tall and Small Cells for MOSFET Scaling
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Solution Overview
Problem
The scaling down of MOSFETs in semiconductor devices leads to deterioration in operational characteristics, necessitating improvements in electrical and reliability performance.
Innovation Solution
A semiconductor device design featuring specific arrangements and overlaps of conductive lines, cells, and patterns, including tall and small cells, with varying widths and connections, to enhance electrical and reliability characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If MOSFETs are scaled down to meet smaller pattern sizes, then device density increases, but operational characteristics deteriorate
Solution Approach 1:
The patent transitions from planar 2D MOSFET structures to three-dimensional FinFET structures with vertical fins extending from the substrate. This dimensional change increases the effective channel area and device density while maintaining acceptable operational characteristics through the fin geometry that provides better gate control.
Solution Approach 2:
The device is divided into multiple fins arranged in parallel, with each fin acting as an independent current path. The gate electrode wraps around each fin, creating segmented control regions that improve overall device performance while increasing density. The conductive lines are also segmented into multiple lower conductive lines (first, second, third) that can be independently optimized.
2Reliability
If multiple conductive lines and cells are arranged to improve electrical characteristics, then device performance improves, but device complexity increases
Solution Approach 1:
The gate electrode structure serves multiple functions: it controls current flow through each fin, provides mechanical support for the vertical structure, and enables wrap-around coverage for improved electrostatic control. The lower conductive lines serve as both electrical interconnects and structural elements that define the active regions. This multi-functionality reduces the need for additional separate components, managing complexity while improving performance.
Solution Approach 2:
Multiple fins are merged into a single integrated device structure under one gate electrode, creating a FinFET that combines the functionality of multiple transistors. The first, second, and third lower conductive lines are merged with the active contact and source/drain patterns to form an integrated electrical pathway. This merging reduces the number of discrete components and simplifies the overall layout while maintaining enhanced electrical characteristics.
Data Source
AI summary
A semiconductor device includes an upper conductive line, a first lower conductive line, a second lower conductive line, and a third lower conductive line arranged in a first direction. The semiconductor device also includes a lower active contact connected to one of the first, second, and third lower conductive lines. Further, the semiconductor device includes a first tall cell, a second tall cell, a first small cell, and a second small cell disposed between the upper conductive line and the first, second, and third lower conductive lines and arranged in the first direction. Each of the first and second tall cells includes a tall pattern and a tall source/drain pattern connected to the tall pattern. Each of the first and second small cells includes a small pattern and a small source/drain pattern connected to the small pattern.