FinFET Standard Cell Design Using Local Layout Effects
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Solution Overview
Problem
The design of FinFET-based standard cells is constrained by high gate capacitance, discrete fin options, and layout-dependent effects, leading to increased complexity and sub-optimal performance, particularly in achieving balanced beta ratios and reducing power consumption.
Innovation Solution
The method involves removing fingers from PFETs in a standard FinFET cell layout, introducing a Half-Double Diffusion Break on the NFET side using a cut-poly layer to isolate PFET and NFET gates, and converting removed PFET fingers into floating gates by shorting their terminals to a common power net, thereby creating a hybrid structure that exploits local layout effects for improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If FinFET structure is used to reduce area occupancy, then area efficiency is improved, but gate capacitance increases leading to higher delay and power consumption
Solution Approach 1:
The patent applies local quality by introducing diffusion breaks at specific locations within the FinFET structure. These diffusion breaks are placed strategically to reduce parasitic capacitance at critical interfaces, thereby lowering overall power consumption while maintaining the area-efficient FinFET configuration.
2Ease of manufacture
If discrete fin options are used for device width selection, then manufacturing simplicity is improved, but design flexibility is reduced making it difficult to achieve optimal beta ratios
Solution Approach 1:
The patent segments the device width into two independent controllable parameters: number of fins and channel width. This segmentation allows designers to independently optimize each parameter to achieve desired beta ratios while maintaining manufacturing simplicity through standardized fin structures.
Solution Approach 2:
The patent enables continuous adjustment of device width by varying the channel width parameter independently from the fin count. This parameter change approach provides design flexibility to achieve optimal beta ratios without compromising manufacturing simplicity.
3Power
If multiple fins are added to increase drive current, then current driving capability is improved, but input capacitance increases leading to higher dynamic power consumption
Solution Approach 1:
The patent changes the channel width parameter to increase drive current instead of simply adding more fins. This parameter change allows achieving higher drive current while controlling input capacitance, thereby reducing dynamic power consumption.
Solution Approach 2:
The patent applies local quality by introducing diffusion breaks at specific locations to reduce parasitic capacitance. This local modification reduces the capacitive loading associated with multiple fins, thereby lowering dynamic power consumption while maintaining high drive current capability.
4Ease of manufacture
If standard FinFET layout is used, then manufacturing process is simplified, but layout dependent effects increase causing design complexity
Solution Approach 1:
The patent applies local quality by introducing diffusion breaks at specific strategic locations within the standard FinFET layout. These localized modifications address layout dependent effects without disrupting the overall simplified manufacturing process, thereby reducing design complexity while maintaining process simplicity.
Data Source
AI summary
Inventive concepts describe a method for high performance standard cell design techniques in FinFET based library using LLE. Inventive concepts describe a fabrication process using a standard FinFET cell layout having double diffusion breaks (DDBs) and single diffusion breaks (SDBs). According to one example embodiment, the method comprises of removing one or more fingers of a P-type FinFet (PFET) from a standard FinFET cell layout. After removing the one or more fingers, a Half-Double Diffusion Break (Half-DDB) is introduced on a N-type FinFET (NFET) side inside a cell boundary using a cut-poly layer. The cut-poly layer not only isolates the PFET and NFET gates and also becomes an integral part of hybrid structure. Further, the removed one or more fingers of PFET gates are converted to two floating PFET gates by shorting a drain terminal and a source terminal of the PFET gate to a common power net.