FINFET Cell Layout With U-Shaped Local Interconnects
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Solution Overview
Problem
The challenge is to improve the characteristics and reduce the area of semiconductor devices with FINFETs while maintaining high integration and efficiency.
Innovation Solution
The semiconductor device incorporates a FINFET configuration with a gate electrode and dummy gate arrangement, where the drain regions of p-channel and n-channel FINFETs are connected through local interconnects forming a U shape, reducing the cell area and increasing integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional planar-type MISFET structure is used, then manufacturing is simpler, but short channel effect cannot be suppressed and current drive power is insufficient
Solution Approach 1:
The patent transitions from a conventional planar two-dimensional structure to a three-dimensional FINFET structure with fins extending vertically from the substrate. This dimensional change enables better gate control over the channel through the wrap-around gate configuration, effectively suppressing short channel effects while maintaining manufacturability through established semiconductor processing techniques.
2Length of moving object
If gate length is reduced according to scaling rule, then device dimension is reduced, but short channel effect worsens and current drive power becomes insufficient
Solution Approach 1:
By introducing vertical fins that extend upward from the substrate, the patent creates a three-dimensional structure where the gate wraps around the fin. This allows the gate length to be reduced in the planar direction while the vertical fin height provides additional control, preventing short channel effects from worsening despite scaling.
Solution Approach 2:
The patent employs a composite structure combining the substrate, vertically extending fins, and wrap-around gate electrodes. This composite architecture enables the device to achieve both reduced gate length for scaling and maintained short channel effect suppression through the multi-component three-dimensional structure.
3Area of stationary object
If device area is reduced for higher integration, then integration density increases, but device characteristics may deteriorate
Solution Approach 1:
The patent utilizes the vertical dimension by extending fins upward from the substrate, allowing the device to achieve higher integration density in the planar area while maintaining device characteristics through the three-dimensional fin structure that provides effective gate control without requiring larger footprint.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces the area of the semiconductor device, enhances integration, and improves carrier mobility due to strain effects, leading to increased ON current and better device performance.
Implementation Method 1
improves carrier mobility due to strain effects
Data Source
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AI summary
An area of a semiconductor device having a FINFET can be reduced. The drain regions of an n-channel FINFET and a p-channel FINFET are extracted by two second local interconnects from a second Y gird between a gate electrode and a dummy gate adjacent thereto, to a third Y grid adjacent to the second Y gird. These second local interconnects are connected by a first local interconnect extending in the X direction in the third Y grid According to such a cell layout, although the number of grids is increased by one because of the arrangement of the first local interconnect, the length in the X direction can be reduced As a result, the cell area of the unit cell can be reduced while a space between the first and second local interconnects is secured.