FinFET Contact Etch Stop Layer Oxidation for Parasitic Capacitance Reduction
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Solution Overview
Problem
The scaling down of Integrated Circuit (IC) manufacturing processes has increased complexity, particularly in the formation of Fin Field-Effect Transistors (FinFETs), where existing methods face challenges in reducing parasitic capacitance and improving AC performance due to the dielectric layers used in FinFET fabrication.
Innovation Solution
The process involves forming a Contact Etch Stop Layer (CESL) with a densification process followed by an oxidation anneal, converting SiN to SiON or SiO2, which reduces the dielectric constant and thickness of the layer adjacent to the gate spacers, thereby reducing parasitic capacitance and enhancing device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional dielectric layers are used in FinFET fabrication, then manufacturing is simpler, but parasitic capacitance increases and AC performance deteriorates
Solution Approach 1:
The patent applies parameter changes by converting the CESL material from silicon nitride (SiN) to silicon oxide (SiO2) through thermal oxidation. This material transformation changes the dielectric constant from approximately 7.5 to 3.9, directly reducing parasitic capacitance and improving AC performance without fundamentally altering the fabrication process flow
Solution Approach 2:
The patent employs strong oxidants (oxygen or water vapor) in a thermal oxidation process to convert the silicon nitride CESL into silicon oxide. This accelerated oxidation approach efficiently transforms the material properties to achieve lower dielectric constant and reduced parasitic capacitance
2Reliability
If CESL thickness is increased to provide better etch stop functionality, then etch protection improves, but parasitic capacitance increases
Solution Approach 1:
The patent changes the material parameter of the CESL from high-k silicon nitride to low-k silicon oxide. This material substitution allows the layer to maintain adequate etch stop functionality while simultaneously reducing the dielectric constant, thereby lowering parasitic capacitance even at the same thickness
Solution Approach 2:
The patent converts the potentially harmful effect of thick dielectric layers (which increase parasitic capacitance) into a benefit by using silicon oxide material. The same physical thickness that would normally increase capacitance now provides etch protection with minimal capacitance penalty due to the material's inherently lower dielectric constant
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces parasitic capacitance and improves the AC and high-speed performance of FinFETs by converting CESL to materials with lower dielectric constants, such as SiON or SiO2, leading to better operational efficiency.
Implementation Method 1
performing an anneal process on the oxide layer and the etch stop layer, wherein the vertical portion has a greater concentration of oxygen than the horizontal portion after the anneal process
Data Source
AI summary
A method includes forming a dummy gate stack on a substrate, forming a spacer layer on the dummy gate stack, forming an etch stop layer over the spacer layer and the dummy gate stack, the etch stop layer comprising a vertical portion and a horizontal portion, and performing a densification process on the etch stop layer, wherein the horizontal portion is denser than the vertical portion after the densification process The method also includes forming an oxide layer over the etch stop layer, performing an anneal process on the oxide layer and the etch stop layer, wherein the vertical portion has a greater concentration of oxygen than the horizontal portion after the anneal process.