FinFET Channel Cladding via Replacement Gate Cavity

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Solution Overview

Problem

The cladding material in the channel region of FinFET semiconductor devices is prone to damage and degradation during the fabrication process, leading to defects and adverse effects on device performance.

Innovation Solution

The method involves forming a sacrificial gate structure, creating a replacement gate cavity, and then forming a replacement epi semiconductor cladding material around a reduced-size fin within this cavity, which reduces the risk of damage and allows for the formation of a stable channel region.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If cladding material is formed early in the fabrication process, then the channel region can be established, but the cladding material becomes prone to damage and degradation during subsequent fabrication steps

Engineering Contradiction:
Improvecladding material integrityVSAvoiddamage and degradation during fabrication
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent applies preliminary action by forming the cladding material last in the fabrication sequence, after the gate structure is already in place. This reverse chronological approach protects the cladding material from damage during subsequent processing steps by ensuring it is formed after critical structures are already protected or removed.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent inverts the conventional fabrication sequence by forming the cladding material after the gate structure rather than before. This inversion of the normal process order resolves the contradiction by eliminating the exposure of cladding material to damaging fabrication steps that occur after its formation in traditional approaches.

Inventive Principle:
Principle #13The other way round (Inversion)

2Device complexity

If a standard-size fin is used in the channel region, then the device structure is simpler, but the channel region is more susceptible to damage during fabrication

Engineering Contradiction:
Improvefin structure complexityVSAvoidchannel region stability
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent applies local quality by creating a reduced-size fin specifically in the channel region under the gate structure, while maintaining standard fin dimensions in other areas. This localized modification protects the vulnerable channel region without requiring changes to the entire fin structure, thus balancing complexity and reliability.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent segments the fin structure into different regions: a reduced-size fin in the channel region and full-size fins in the source/drain regions. This segmentation allows the vulnerable channel area to be protected while maintaining the structural integrity and function of the overall fin system.

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach minimizes damage to the cladding material, enhancing the reliability and performance of the semiconductor device by forming a stable channel region with improved structural integrity.

Implementation Method 1

The cladding material 17 is typically an epi semiconductor material, such as silicon germanium, that is formed on the fin 16 by performing known epi deposition processes.

Methodology Applied
Scientific EffectEpitaxy: Epitaxy

Data Source

PatentUS9508853B2Channel cladding last process flow for forming a channel region on a FinFET device having a reduced size fin in the channel region
Publication Date: 2016.11.29 GLOBALFOUNDRIES US INC
  • US9508853B2 patent drawing
  • US9508853B2 patent drawing
  • US9508853B2 patent drawing

AI summary

One method of forming epi semiconductor cladding materials in the channel region of a semiconductor device is disclosed which includes forming a sacrificial gate structure around a portion of an initial fin, forming a sidewall spacer adjacent opposite sides of the sacrificial gate structure and removing the sacrificial gate structure so as to thereby define a replacement gate cavity, performing an etching process through the replacement gate cavity to remove portions of the initial fin so as to thereby define a reduced size fin and recesses under the sidewall spacers, forming at least one replacement epi semiconductor cladding material around the reduced size fin in the replacement gate cavity and in the recesses under the sidewall spacers, and forming a replacement gate structure within the replacement gate cavity around the at least one replacement epi semiconductor cladding material.