FinFET Channel Height Control via Spacer-Mediated Epitaxy

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Solution Overview

Problem

The manufacturing process of FinFET devices faces challenges in achieving precise control over the channel structure, particularly in maintaining the height consistency of flank and channel portions of the fins, which affects electrical performance and increases production costs due to the need for complex etching processes and multiple masks.

Innovation Solution

The method involves forming fins with protruded channel and flank portions of equal height from the insulators, using a spacer material layer to selectively remove and expose the flank portions, followed by epitaxial growth of strained material on the flank portions, and finally forming gate stacks over the channel portions, eliminating the need for recessing the fins and additional etching steps.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If complex etching processes and multiple masks are used to maintain fin height consistency, then manufacturing precision is improved, but device complexity and production cost increase

Engineering Contradiction:
Improvefin height consistencyVSAvoidetching process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The spacer layer is formed on the fins before the gate structure is created, establishing a reference height that guides subsequent processing steps. This preliminary structuring enables precise fin height control without requiring complex etching sequences

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The spacer layer acts as an intermediary element between the fin formation and gate structure steps. It provides a physical template that mediates the height relationship between fins and gate, eliminating the need for multiple masks and complex etching processes

Inventive Principle:
Principle #24Intermediary (Mediator)

2Manufacturing precision

If complex etching processes and multiple masks are used to maintain fin height consistency, then manufacturing precision is improved, but production cost increases

Engineering Contradiction:
Improvefin height consistencyVSAvoidproduction cost
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The spacer layer is formed on the fins before the gate structure is created, establishing a reference height that guides subsequent processing steps. This preliminary structuring enables precise fin height control without requiring complex etching sequences

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The spacer layer acts as an intermediary element between the fin formation and gate structure steps. It provides a physical template that mediates the height relationship between fins and gate, eliminating the need for multiple masks and complex etching processes

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances electrical performance by reducing leakage current, alleviating short channel effects, and improving the on/off current ratio while simplifying the manufacturing process and reducing production costs by avoiding extra etching and mask requirements.

Implementation Method 1

The spacer material layer is removed to expose top surfaces of the flank portions and to expose a top surface of the at least one stack strip structure

Methodology Applied
Scientific EffectEtching:

Implementation Method 2

epitaxial growth of strained material on the flank portions

Methodology Applied
Scientific EffectEpitaxial growth: Epitaxy

Data Source

PatentUS10153278B1Fin-type field effect transistor structure and manufacturing method thereof
Publication Date: 2018.12.11 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US10153278B1 patent drawing
  • US10153278B1 patent drawing
  • US10153278B1 patent drawing

AI summary

A fin-type field effect transistor comprising a substrate, at least one gate stack, spacers and epitaxy material portions is described. The substrate has fins and insulators located between the fins, and the fins comprise channel portions and flank portions beside the channel portions, the flank portions and the channel portions of the fins are protruded from the insulators, the flank portions of the fins and the channel portions of the fins have substantially a same height from top surfaces of the insulators, and each of the flank portions of the fins has a top surface and side surfaces adjoining the top surface. The at least one gate stack is disposed over the substrate, disposed on the insulators and over the channel portions of the fins. The spacers are disposed on the side surfaces of the flank portions of the fins. The epitaxy material portions are located above the top surfaces of the flank portions of the fins.