FinFET Channel Isolation via Epi Etch Stop Layer
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In FinFET semiconductor devices, forming an isolated channel region is challenging due to the short channel effect, which degrades the performance of transistors with reduced channel lengths, and current manufacturing methods lack a reliable and repeatable methodology to achieve this isolation effectively.
Innovation Solution
The method involves forming a fin structure with multiple epi semiconductor layers, creating a sacrificial gate structure, and using epitaxial deposition to form an epi etch stop layer, followed by etching processes to define a fin cavity and channel cavity, and filling the channel cavity with insulating material to form a replacement gate structure, ensuring effective isolation of the channel region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the channel length of FET is reduced to improve switching speed and increase transistor density, then the operating speed and density are improved, but the short channel effect worsens, degrading the transistor's switching characteristic
Solution Approach 1:
The patent transitions from a planar FET structure to a FinFET structure with a vertically extending channel. The channel is formed as a fin that rises from the substrate, allowing the gate to wrap around three sides of the channel (tri-gate configuration). This dimensional change from 2D planar to 3D vertical structure improves gate control over the channel, effectively suppressing short channel effects even at reduced channel lengths while maintaining high switching speed and density.
2Reliability
If epitaxial growth is performed to increase fin size in source/drain regions, then source/drain resistance is reduced, but the fins in source/drain regions may merge together, causing loss of channel isolation
Solution Approach 1:
The patent performs epitaxial growth to increase fin size in the source/drain regions before forming the gate structure. By conducting this growth operation beforehand, the fins are enlarged to reduce source/drain resistance and improve contact reliability. The gate structure is then formed to define the channel region, ensuring that even with enlarged fins, proper channel isolation is maintained through the gate's positioning and the subsequent formation of channel isolation structures.
3Ease of manufacture
If conventional manufacturing methods are used for FinFET devices, then basic device functionality is achieved, but there is no reliable and repeatable methodology to achieve effective channel region isolation
Solution Approach 1:
The patent employs a segmented approach to channel isolation by forming separate channel isolation structures in the channel region distinct from the source and drain regions. This segmentation allows independent optimization of source/drain contact properties and channel isolation properties. The method introduces specific process steps for forming channel isolation structures that are reliably repeatable and effectively isolate the channel region, addressing the limitations of conventional methods.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the isolation of the channel region, reducing leakage current and improving the operational characteristics of FinFET devices by effectively addressing the short channel effect and increasing the reliability of the manufacturing process.
Implementation Method 1
performing an epitaxial deposition process to form an epi etch stop layer on the exposed edges of the fin structure positioned under the sidewall spacer and within the fin cavity
Data Source
AI summary
One method disclosed includes, among other things, forming a fin structure comprised of a semiconductor material, a first epi semiconductor material and a second epi semiconductor material, forming a sacrificial gate structure above the fin structure, forming a sidewall spacer adjacent the sacrificial gate structure, performing at least one etching process to remove the portions of the fin structure positioned laterally outside of the sidewall spacer so as to thereby define a fin cavity in the source/drain regions of the device and to expose edges of the fin structure positioned under the sidewall spacer, and performing an epitaxial deposition process to form an epi etch stop layer on the exposed edges of the fin structure positioned under the sidewall spacer and within the fin cavity.