FinFET Channel Length Control via Sidewall Spacer Etching
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current methods for fabricating FinFET structures struggle with forming gate structures of different widths and channel lengths, leading to static current leakage and high variability in transistor performance, especially as semiconductor structures approach 22 nanometer and 15 nanometer technology nodes.
Innovation Solution
The method involves forming sidewall spacers of varying widths over mandrels using a hard mask layer and etching techniques to create gate structures with different widths, allowing for the fabrication of FinFETs with multiple channel lengths, reducing variability and leakage by eliminating the need for multiple photoresist masks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithographic fabrication methods are used to form gate structures, then manufacturing simplicity is maintained, but all transistors must have the same channel length, leading to static current leakage and high variability in transistors that do not require short channel lengths
Solution Approach 1:
The patent segments the gate structure fabrication by forming different channel length regions separately. First, a first set of mandrels is formed to define first channel lengths, then a second set of mandrels is formed to define second channel lengths. This segmentation allows each region to be optimized independently, resolving the contradiction between precise channel length control and fabrication simplicity.
Solution Approach 2:
The patent applies preliminary action by forming mandrels and sidewall spacers before final gate electrode deposition. The sidewall spacers are formed around the mandrels to pre-establish the precise channel length dimensions before the gate material is deposited, ensuring accurate channel length control is built into the structure early in the fabrication process.
2Productivity
If small channel length FinFETs are fabricated to increase current drive strength and operating frequency, then device performance is improved, but static current leakage increases and channel length variability increases
Solution Approach 1:
The patent applies local quality by creating different channel length regions within the same semiconductor device. Critical timing transistors use short channel lengths for high performance, while non-critical transistors use longer channel lengths for lower leakage. This local differentiation resolves the contradiction by allowing each transistor to have the optimal channel length for its specific function.
Solution Approach 2:
The patent changes the channel length parameter locally across different transistor regions. By forming mandrels and sidewall spacers with different dimensions in different areas, the channel length parameter is varied to optimize performance for critical transistors while minimizing leakage for non-critical transistors, resolving the performance-leakage tradeoff.
3Adaptability or versatility
If multiple photoresist masks are used to form gate structures with different widths, then different channel lengths can be achieved, but manufacturing complexity and process variability increase
Solution Approach 1:
The patent uses sidewall spacers as intermediary structures between the mandrels and the final gate electrodes. The sidewall spacers are formed by depositing material around the mandrels and then anisotropically etching, creating precise spacing that defines the channel length. This intermediary approach eliminates the need for multiple photoresist masks while achieving different channel lengths through a single mask process.
Solution Approach 2:
The patent replaces the mechanical photoresist mask system with a self-aligned sidewall spacer formation process. Instead of using multiple photoresist masks to define different channel lengths, the process uses conformal deposition and anisotropic etching to automatically create the spacing, substituting a more precise and simpler manufacturing approach.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the simultaneous formation of FinFET structures with varying channel lengths, improving device performance by reducing static leakage and power consumption, and allowing for the fabrication of both N-channel and P-channel FinFETs with different channel lengths.
Implementation Method 1
The first sidewall spacer-forming material and the second sidewall-spacer material are anisotropically etched to form first sidewall spacers about sidewalls of each of the first plurality of mandrels and second sidewall spacers about sidewalls of each of the second plurality of mandrels.
Data Source
AI summary
Methods for fabricating FinFET structures having gate structures of different gate widths are provided. The methods include the formation of sidewall spacers of different thicknesses to define gate structures of the FinFET structures with different gate widths. The width of a sidewall spacer is defined by the height of the structure about which the sidewall spacer is formed, the thickness of the sidewall spacer material layer from which the spacer is formed, and the etch parameters used to etch the sidewall spacer material layer. By forming structures of varying height, forming the sidewall spacer material layer of varying thickness, or a combination of these, sidewall spacers of varying width can be fabricated and subsequently used as an etch mask so that gate structures of varying widths can be formed simultaneously.