FinFET Channel Reshaping for Reduced DIBL and Leakage
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Solution Overview
Problem
Conventional planar FETs face challenges such as sub-threshold swing degradation, significant drain-induced barrier lowering, and fluctuation of device characteristics when reduced in size, which finFETs aim to overcome.
Innovation Solution
The formation of finFETs involves creating fins on a substrate with a gate dielectric and gate electrode, along with epitaxial source/drain regions and re-shaping the channel region to achieve improved electrical characteristics, using techniques like etching and annealing to form a trapezoidal or triangular cross-section.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If planar FETs are reduced in size to increase density, then device footprint is reduced, but sub-threshold swing degradation and drain-induced barrier lowering occur
Solution Approach 1:
The patent transitions from planar 2D channel structure to a 3D fin structure with vertical channels. The fin rises vertically from the substrate, creating a three-dimensional configuration where the channel extends in the vertical dimension. This dimensional change increases the effective channel area without proportionally increasing the footprint, while improving gate control over the channel to reduce DIBL and sub-threshold swing degradation.
Solution Approach 2:
The gate structure wraps around the fin channel in a surround-gate configuration, with the gate dielectric and gate electrode enveloping the fin from multiple sides. This nested arrangement provides enhanced gate control over the channel compared to conventional planar gates, improving electrical characteristics while maintaining compact footprint.
2Reliability
If fins are re-shaped to improve electrical characteristics, then surface roughness and mobility are enhanced, but manufacturing complexity increases
Solution Approach 1:
The fin structure is re-shaped with curved surfaces instead of straight vertical walls. The re-shaping process creates specific curvature profiles on the fin sidewalls that enhance carrier mobility and electrical performance. This curvature modification transforms the originally planar fin geometry into a optimized three-dimensional shape that improves device characteristics.
Solution Approach 2:
The re-shaping process modifies geometric parameters of the fin structure, including sidewall angles, curvature radii, and surface profiles. By changing these geometric parameters through controlled etching and annealing processes, the patent optimizes carrier transport properties and electrical performance while managing manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the electrical performance and mobility of finFETs, addressing the limitations of conventional planar FETs by improving surface roughness and device reliability.
Implementation Method 1
a gate dielectric 36 is along sidewalls and over a top surface of the fin 34, and a gate electrode 38 is over the gate dielectric 36
Implementation Method 2
The intermediate stages of forming the finFETs are illustrated
Data Source
AI summary
A finFET and methods for forming a finFET are disclosed. A structure comprises a substrate, a fin, a gate dielectric, and a gate electrode. The substrate comprises the fin. The fin has a major surface portion of a sidewall, and the major surface portion comprises at least one lattice shift. The at least one lattice shift comprises an inward or outward shift relative to a center of the fin. The gate dielectric is on the major surface portion of the sidewall. The gate electrode is on the gate dielectric.