FinFET Channel Stacks With Alternating Recessed Regions for Mobility Control
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Solution Overview
Problem
As the scale of fin width in FinFETs decreases, channel width variations can lead to mobility loss, necessitating the development of alternative transistor structures like nano-FETs that improve electrostatic control and mitigate leakage currents.
Innovation Solution
The introduction of interbridge channels between neighboring nanostructure channels in nano-FETs, specifically localized to the periphery region, enhances on-current by reducing concave corners and strengthening gate control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If fin width is decreased to improve integration density, then more components can be integrated into a given area, but channel width variations lead to mobility loss
Solution Approach 1:
The channel is segmented into multiple narrow fins instead of a single wide channel. This segmentation allows for higher integration density while maintaining electrostatic control through the gate, preventing mobility loss that would occur in scaled-down single-channel structures.
Solution Approach 2:
The transistor structure transitions from a planar two-dimensional channel to a three-dimensional fin structure. The fins extend vertically from the substrate, adding a third dimension that enables better gate control and maintains carrier mobility while achieving higher integration density.
2Ease of manufacture
If conventional FinFET structure is used, then manufacturing is relatively simple, but electrostatic control is insufficient and leakage currents are high
Solution Approach 1:
The channel is divided into multiple discrete fins, which improves electrostatic control by allowing the gate to more effectively modulate the channel conductivity. This segmentation enables better control over carrier flow while maintaining compatibility with existing manufacturing processes.
Solution Approach 2:
The fin structure creates localized regions of high electric field concentration at the fin tips and along the fin surfaces. This local quality enhancement improves electrostatic control and reduces leakage currents in specific critical regions of the channel.
3Power
If interbridge channels are introduced to enhance on-current, then electron density improves, but device complexity increases
Solution Approach 1:
The interbridge channels are merged with the existing fin structure to form an integrated channel architecture. This combining approach enhances on-current by providing additional conduction paths while avoiding the need for entirely separate, complex channel structures.
Solution Approach 2:
The interbridge channels extend in the vertical dimension, connecting adjacent fins through the gate dielectric layer. This three-dimensional configuration increases on-current capability without significantly increasing planar device complexity, as the additional channels are formed vertically rather than laterally.
Data Source
AI summary
A device includes a first channel structure, a second channel structure, and a gate structure. The first channel structure connects a first source region and a first drain region, and includes alternating stacking first semiconductor layers and second semiconductor layers. The second semiconductor layers have a width smaller than a width of the first semiconductor layers. The second channel structure connects a second source region and a second drain region. The second channel structure includes alternating stacking third semiconductor layers and fourth semiconductor layers. The fourth semiconductor layers have a width smaller than a width of the third semiconductor layers. The gate structure wraps around the first and second channel structures.