FinFET Channel Strain Control via Segmented Buried Layers

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Solution Overview

Problem

Conventional techniques for manufacturing nonplanar transistors, such as FinFETs, face challenges in forming compound semiconductor channels and insulating features due to lattice structure differences, leading to undesirable channel strains and lattice defects, which affect device performance and reliability.

Innovation Solution

The use of individually adapted buried layers, configured to impart specific strains and reduce lattice dislocations, allows for the formation of FinFETs with optimized channel regions, using techniques like epitaxial growth and oxidation to create suitable insulating layers that isolate the FinFETs from the substrate, enabling improved carrier mobility and reduced leakage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If conventional techniques are used to form compound semiconductor channels on elementary semiconductor substrates, then manufacturing simplicity is maintained, but channel strain control deteriorates and lattice defects increase

Engineering Contradiction:

Improvemanufacturing simplicityVSAvoidchannel strain control

Core Design Contradiction:

Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent divides the semiconductor structure into distinct segments: an elementary semiconductor substrate and a compound semiconductor channel layer. By segmenting the structure and introducing intermediate layers, the patent enables independent optimization of each layer's properties, allowing precise control of channel strain while maintaining manufacturing feasibility through standardized fabrication processes.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces intermediate layers between the elementary semiconductor substrate and the compound semiconductor channel. These intermediary layers act as buffers that mediate the lattice mismatch between dissimilar materials, enabling the formation of high-quality compound semiconductor channels on elementary semiconductor substrates without excessive lattice defects or uncontrolled strain.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Ease of manufacture

If conventional techniques are used to form insulating features, then process simplicity is maintained, but isolation effectiveness deteriorates due to lattice structure differences

Engineering Contradiction:

Improveprocess simplicityVSAvoidisolation effectiveness

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

The patent applies local quality by forming insulating features with specific material compositions and structural characteristics tailored to the local requirements at the interface between compound semiconductor channels and elementary semiconductor substrates. This localized optimization ensures effective electrical isolation while accounting for the lattice structure differences that conventional uniform approaches cannot address.

Inventive Principle:

Principle #3Local quality

3Device complexity

If FinFET structures are formed without adapted buried layers, then device complexity is reduced, but carrier mobility deteriorates due to uncontrolled channel strain

Engineering Contradiction:

Improvestructure simplicityVSAvoidcarrier mobility

Core Design Contradiction:

Device complexityVSReliability

Solution Approach 1:

The patent utilizes parameter changes by carefully controlling the composition, thickness, and crystal structure of buried layers beneath the FinFET channels. By adjusting these parameters, the patent optimizes channel strain to enhance carrier mobility in the FinFET devices, achieving high performance without significantly increasing device complexity.

Inventive Principle:

Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances the performance of FinFETs by controlling channel strain, reducing lattice dislocations, and enabling the use of materials with greater lattice structure differences, resulting in improved carrier mobility and reduced leakage, thus addressing the limitations of conventional techniques.

Implementation Method 1

individually adapted buried layers, configured to impart specific strains and reduce lattice dislocations

Methodology Applied

Scientific EffectLattice strain:

Implementation Method 2

using techniques like epitaxial growth and oxidation to create suitable insulating layers

Methodology Applied

Scientific EffectEpitaxy: Epitaxy

Implementation Method 3

using techniques like epitaxial growth and oxidation to create suitable insulating layers

Methodology Applied

Scientific EffectOxidation: Oxidation

Data Source

PatentUS10103264B2Channel strain control for nonplanar compound semiconductor devices

Publication Date: 2018.10.16 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A circuit device having differently-strained NMOS and PMOS FinFETs is provided. In an exemplary embodiment, a semiconductor device includes a substrate with a first fin structure and a second fin structure formed thereup. The first fin structure includes opposing source/drain regions disposed above a surface of the substrate; a channel region disposed between the opposing source/drain regions and disposed above the surface of the substrate; and a first buried layer disposed between the channel region and the substrate. The first buried layer includes a compound semiconductor oxide. The second fin structure includes a second buried layer disposed between the substrate and a channel region of the second fin structure, such that the second buried layer is different in composition from the first. For example, the second fin structure may be free of the compound semiconductor oxide.