FinFET Channel Width Control via Doping Depth

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Solution Overview

Problem

Conventional fin-type field effect transistors face challenges in manufacturing devices with proper channel widths due to uniform fin heights, limiting flexibility and efficiency in reducing leakage current and increasing on-current.

Innovation Solution

The fin-type field effect transistor incorporates a blocking region with a higher doping concentration than the channel region, allowing for varying channel widths by adjusting the doping depth, enabling flexible channel width determination and improved performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If the fin-type structures all have the same height due to manufacturing factors, then the manufacturing process is simple, but the channel width of the FinFET cannot be flexibly adjusted

Engineering Contradiction:
Improvemanufacturing simplicityVSAvoidchannel width adjustability
Core Design Contradiction:
Ease of manufactureVSAdaptability or versatility

Solution Approach 1:

The patent applies local quality by creating blocking regions with different doping concentrations at specific locations within the fin-type structures. The blocking regions have a first doping concentration that differs from the channel region's second doping concentration, allowing selective control of channel width through doping depth adjustment while maintaining uniform fin heights, thus resolving the contradiction between manufacturing simplicity and channel width adjustability

Inventive Principle:
Principle #3Local quality

2Device complexity

If the channel width is determined by the number of fin-type structures, then the structure is simple, but it is difficult to manufacture FinFETs with proper channel width for any requests

Engineering Contradiction:
Improvestructural complexityVSAvoidchannel width customization
Core Design Contradiction:
Device complexityVSAdaptability or versatility

Solution Approach 1:

The patent changes the parameter of doping depth to control channel width. By adjusting the doping depth of the blocking regions, the channel width can be precisely controlled without changing the number or physical dimensions of the fin-type structures. This maintains simple device structure while enabling flexible channel width customization for different applications

Inventive Principle:
Principle #35Parameter changes

3Object-generated harmful factors

If the blocking region doping concentration is increased, then the leakage current is reduced, but the manufacturing precision requirement increases

Engineering Contradiction:
Improveleakage currentVSAvoiddoping depth control
Core Design Contradiction:
Object-generated harmful factorsVSManufacturing precision

Solution Approach 1:

The patent performs preliminary doping to create blocking regions with high doping concentration before forming the gate structure. This preliminary action establishes the blocking regions that will prevent leakage current, and the doping depth is controlled during this initial step to define the future channel width, thereby reducing leakage current while managing manufacturing precision requirements through process sequencing

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS8803247B2Fin-type field effect transistor
Publication Date: 2014.08.12 UNITED MICROELECTRONICS CORP
  • US8803247B2 patent drawing
  • US8803247B2 patent drawing
  • US8803247B2 patent drawing

AI summary

A fin-type field effect transistor including at least one fin-type semiconductor structure, a gate strip and a gate insulating layer is provided. The fin-type semiconductor structure is doped with a first type dopant and has a block region with a first doping concentration and a channel region with a second doping concentration. The first doping concentration is larger than the second doping concentration. The blocking region has a height. The channel region is configured above the blocking region. The gate strip is substantially perpendicular to the fin-type semiconductor structure and covers above the channel region. The gate insulating layer is disposed between the gate strip and the fin-type semiconductor structure.