FinFET CMOS Isolation Layout Using Single and Double Diffusion Breaks
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Solution Overview
Problem
Conventional FinFET CMOS circuits face performance limitations due to varying performance characteristics between P-type and N-type FinFETs, which are attributed to conventional fabrication processes, leading to increased current leakage and reduced threshold voltage.
Innovation Solution
Employing single and double diffusion breaks (SDB and DDB) isolation structures in FinFET CMOS circuits to electrically isolate P-type and N-type FinFETs, allowing each to achieve better performance under stress applied by their respective isolation structures, while using conventional fabrication processes to avoid increased costs and complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional fabrication processes are used to manufacture FinFET CMOS circuits, then manufacturing simplicity is maintained, but performance limitations occur due to varying characteristics between P-type and N-type FinFETs
Solution Approach 1:
The patent applies different diffusion break structures (single diffusion break for P-type FinFETs, double diffusion break for N-type FinFETs) to different transistor types within the same CMOS circuit. This local differentiation allows each transistor type to receive optimized isolation treatment tailored to its specific performance requirements, thereby improving overall performance consistency without requiring complete process redesign
Solution Approach 2:
The invention segments the diffusion break isolation approach into two distinct configurations: single diffusion break (SDB) for P-type FinFETs and double diffusion break (DDB) for N-type FinFETs. This segmentation enables independent optimization of each transistor type's electrical isolation characteristics, addressing their different performance needs while maintaining a unified fabrication framework
2Productivity
If channel length in planar transistors is reduced to increase transistor density, then drive strength increases and parasitic capacitances decrease, but short channel effects occur causing increased current leakage and reduced threshold voltage
Solution Approach 1:
The patent transitions from planar transistor geometry to three-dimensional FinFET structure with wrap-around gates. This dimensional change provides superior electrostatic control over the channel, effectively suppressing short channel effects and current leakage while enabling continued scaling of channel length to increase transistor density
Solution Approach 2:
The diffusion break structures serve as intermediary isolation elements between adjacent FinFETs. By introducing these intermediate isolation regions, the patent achieves electrical isolation that prevents harmful interactions and leakage currents while maintaining the scaled-down channel dimensions needed for high density
3Reliability
If P-type and N-type FinFETs are fabricated using conventional processes, then fabrication simplicity is maintained, but one transistor type limits the overall CMOS circuit performance due to varying performance characteristics
Solution Approach 1:
The patent implements transistor-type-specific diffusion break configurations: single diffusion break structures for P-type FinFETs and double diffusion break structures for N-type FinFETs. This local quality differentiation allows each transistor type to achieve optimized electrical characteristics and isolation, improving overall CMOS circuit performance while integrating seamlessly into conventional fabrication workflows
Solution Approach 2:
The invention modifies the diffusion break isolation parameters (single vs. double breaks) based on transistor type requirements. By changing the diffusion break configuration parameter according to whether the FinFET is P-type or N-type, the patent optimizes performance for each device type while maintaining compatibility with existing manufacturing processes
Data Source
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Figure 3A~3B
AI summary
Fin Field Effect Transistor (FET) (FinFET) complementary metal oxide semiconductor (CMOS) circuits with single and double diffusion breaks for increased performance are disclosed. In one aspect, a FinFET CMOS circuit employing single and double diffusion breaks includes a P-type FinFET that includes a first Fin formed from a semiconductor substrate and corresponding to a P-type diffusion region. The FinFET CMOS circuit includes an N-type FinFET that includes a second Fin formed from the semiconductor substrate and corresponding to an N-type diffusion region. To electrically isolate the P-type FinFET, first and second single diffusion break (SDB) isolation structures are formed in the first Fin on either side of a gate of the P-type FinFET. To electrically isolate the N-type FinFET, first and second double diffusion break (DDB) isolation structures are formed in the second Fin on either side of a gate of the N-type FinFET.