FinFET CMOS Gate Spacer Uniformity via Single Lithography
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Solution Overview
Problem
Conventional methods for forming complementary finFETs with in-situ doped source/drain regions face challenges such as uneven gate spacer thickness, differing anneal temperatures, and residual hard mask ridges between nFET and pFET pairs due to dual lithography steps and multiple hard mask layers.
Innovation Solution
A process involving a carbon-doped silicon layer on both nFET and pFET source/drain regions, with simultaneous epitaxial growth of tensile-strain in-situ phosphorous doped silicon for nFET and compressive-strain in-situ boron doped SiGe for pFET, and a single anneal to activate dopants, ensuring uniform gate spacers and eliminating hard mask ridges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If dual lithography steps with multiple hard mask layers are used to form complementary finFETs, then separate strain engineering for nFET and pFET can be achieved, but uneven gate spacer thickness and residual hard mask ridges appear between adjacent transistors
Solution Approach 1:
The patent merges the formation of gate spacers for both nFET and pFET into a single lithography step using one hard mask layer. The gate spacer material is deposited conformally across the entire gate structure, and a single etch step forms spacers of uniform thickness on both transistor types, eliminating the thickness variation caused by sequential processing
Solution Approach 2:
The patent employs a universal gate spacer formation process that simultaneously serves both nFET and pFET devices. A single hard mask pattern and etch process creates gate spacers for both transistor types with identical dimensions, making the process universally applicable to complementary finFET pairs without requiring device-specific processing variations
2Reliability
If separate epitaxial growth steps are performed for nFET and pFET source/drain regions, then appropriate strain can be applied to each transistor type, but process complexity and manufacturing steps increase
Solution Approach 1:
The patent applies local quality by performing separate epitaxial growth steps for nFET and pFET source/drain regions. Each transistor type receives a tailored epitaxial process: nFET regions undergo phosphorus-doped silicon epitaxy to induce tensile strain, while pFET regions undergo boron-doped silicon germanium epitaxy to induce compressive strain, with each step optimized for the specific device requirements
Solution Approach 2:
The patent segments the epitaxial processing into distinct steps for nFET and pFET devices. The first epitaxial step deposits strained silicon for nFET source/drain regions, and the second epitaxial step deposits SiGe for pFET source/drain regions, allowing independent optimization of each transistor type's strain characteristics
3Reliability
If pFET source/drain region is formed first, then compressive strain can be applied to pFET channel, but the drive-in anneal temperature must be higher than for nFET, broadening dopant front at extension junction
Solution Approach 1:
The patent performs the drive-in anneal for pFET extension regions before forming the nFET source/drain regions. By conducting the high-temperature anneal to activate boron dopants and form pFET extensions first, the process establishes the pFET dopant profile before subsequent nFET processing, preventing dopant front broadening that would occur if nFET regions were formed first and required lower temperature anneals
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in improved finFET performance by maintaining uniform gate spacer thickness and dopant activation across both types of transistors, reducing the need for dual anneals and eliminating residual hard mask material, thereby enhancing short-channel control and mobility.
Implementation Method 1
simultaneous epitaxial growth of tensile-strain in-situ phosphorous doped silicon for nFET and compressive-strain in-situ boron doped SiGe for pFET
Implementation Method 2
tensile-strain in-situ phosphorous doped silicon
Implementation Method 3
in-situ phosphorous doped silicon
Implementation Method 4
compressive-strain in-situ boron doped SiGe
Implementation Method 5
in-situ boron doped SiGe
Implementation Method 6
a single anneal to activate dopants
Implementation Method 7
drive-in anneal to activate the extension
Data Source
AI summary
According to an embodiment, the invention provides an nFET/pFET pair of finFETs formed on a gate stack. At least one fin extends into a source drain region of each of the FET pair and a carbon doped silicon (Si:C) layer is formed on each such fin. Another aspect of the invention is a process flow to enable dual in-situ doped epitaxy to fill the nFET and pFET source drain with different epi materials while avoiding a ridge in the hard cap on the gate between the pair of finFETS. The gate spacer in both of the pair can be the same thickness. The extension region of both of the pair of finFETs can be activated by a single anneal.