FinFET CMP Planarization Without Hard Mask Scratching

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Solution Overview

Problem

In semiconductor manufacturing, the chemical-mechanical polishing (CMP) process for FinFETs faces challenges such as uneven topography and increased surface scratches due to the hard mask layer, leading to variations in critical dimension (CD) and potential peeling defects from unremoved slurry residues.

Innovation Solution

The removal of the hard mask layer prior to CMP, combined with the use of a specific CMP slurry composition that facilitates easier slurry removal and adjusts the polish rate, results in a more balanced loading effect and reduced surface scratches, achieving uniform topography and reduced CD variations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If the hard mask layer is retained during CMP process, then the polishing structure is maintained, but surface scratches increase and topography uniformity deteriorates

Engineering Contradiction:
Improvetopography uniformityVSAvoidsurface scratches
Core Design Contradiction:
Manufacturing precisionVSObject-affected harmful factors

Solution Approach 1:

The hard mask layer is removed before the CMP process to prevent it from causing surface scratches and loading effects during polishing. This preliminary removal action eliminates the source of harmful factors before the main polishing operation begins, ensuring uniform topography without the negative effects of the hard mask layer present during CMP.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If conventional CMP slurry is used, then the polishing process proceeds, but slurry removal becomes difficult and peeling defects occur

Engineering Contradiction:
Improveslurry removal efficiencyVSAvoidpeeling defects
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The CMP slurry composition is modified by adjusting pH levels and adding specific chemicals to change its properties. These parameter changes make the slurry easier to remove from the wafer surface after polishing, preventing peeling defects while maintaining effective polishing performance during the process.

Inventive Principle:
Principle #35Parameter changes

3Manufacturing precision

If the hard mask layer is present during CMP, then the polishing structure is complete, but the loading effect becomes unbalanced and polish rate varies

Engineering Contradiction:
Improvepolish rate uniformityVSAvoidloading effect balance
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The hard mask layer is extracted or removed from the system before the CMP process begins. This eliminates the unbalanced loading effect that the hard mask layer would create during polishing, allowing for uniform material removal rates across different areas of the wafer without the complicating presence of the mask layer.

Inventive Principle:
Principle #2Taking out (Extraction)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances the uniformity of the wafer's topography and reduces the variation in smallest geometrical features, minimizing peeling defects and improving the CMP process's sensitivity to polishing time.

Implementation Method 1

a chemical-mechanical polishing (CMP) process is subsequently performed to remove excess portions of the second epitaxial layer

Methodology Applied
Scientific EffectChemical-mechanical polishing:

Data Source

PatentUS12131911B2CMP process and methods thereof
Publication Date: 2024.10.29 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12131911B2 patent drawing
  • US12131911B2 patent drawing
  • US12131911B2 patent drawing

AI summary

A method of forming a semiconductor device includes forming a first epitaxial layer over a substrate to form a wafer, depositing a dielectric layer over the first epitaxial layer, patterning the dielectric layer to form an opening, etching the first epitaxial layer through the opening to form a recess, forming a second epitaxial layer in the recess, etching the dielectric layer to expose a top surface of the first epitaxial layer, and planarizing the exposed top surface of the first epitaxial layer and a top surface of the second epitaxial layer.