FinFET Composite Liner Structure to Prevent Fin Liner Crystallization
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Solution Overview
Problem
The crystallization of amorphous silicon liners in FinFET devices during thermal processes leads to defects and constraints on low-temperature processing, affecting yield and critical dimension stability.
Innovation Solution
A surface treatment process converts an upper layer of the amorphous silicon liner into a dielectric conversion layer, such as oxide or nitride, using oxygen or ammonia-containing gases or plasmas, preventing crystallization and allowing higher-temperature thermal processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If amorphous silicon liner is used in FinFET devices, then low-temperature processing is enabled, but crystallization during thermal processes causes defects and yield loss
Solution Approach 1:
A liner formation process is performed in advance before subsequent thermal processing steps. The liner is deposited conformally over the fin structure at low temperature, establishing a protective layer that prevents crystallization during later high-temperature processes such as source/drain formation and annealing
Solution Approach 2:
The amorphous silicon liner acts as an intermediary protective layer between the fin structure and the thermal processing environment. This intermediate layer prevents direct thermal damage and crystallization of the underlying structure, enabling high-temperature processing while maintaining material integrity
2Adaptability or versatility
If amorphous silicon liner is used, then processing flexibility is improved, but critical dimension stability deteriorates due to crystallization defects
Solution Approach 1:
The liner is formed in advance to establish a stable protective barrier before subsequent processing steps. This preliminary formation ensures that critical dimensions are locked in place and protected from thermal-induced changes during later high-temperature processes
Solution Approach 2:
The liner serves as an intermediary protective barrier that maintains critical dimension stability. By positioning this stable layer between the fin structure and the thermal environment, the liner prevents dimensional drift and maintains manufacturing precision throughout subsequent processing
3Adaptability or versatility
If higher-temperature thermal processes are performed, then processing options are expanded, but liner crystallization causes defects
Solution Approach 1:
The amorphous silicon liner is deposited in advance to create a thermally stable protective layer. This preliminary formation enables subsequent high-temperature processes such as source/drain epitaxial growth, laser annealing, and rapid thermal annealing without causing liner crystallization defects
Solution Approach 2:
The liner acts as a thermal intermediary that decouples the fin structure from harmful thermal effects. This intermediary layer absorbs and dissipates thermal energy, preventing the liner itself from crystallizing even when exposed to high-temperature processing conditions that expand process options
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach maintains the integrity of the liner, reduces defects, and enables wider processing options without compromising critical dimensions, thereby improving yield and processing flexibility.
Implementation Method 1
converting a top portion of the liner into a dielectric conversion layer, such as an oxide or a nitride, of the liner
Implementation Method 2
using oxygen or ammonia-containing gases or plasmas
Data Source
AI summary
A method of forming a semiconductor device includes forming a fin protruding above a substrate; forming a liner over the fin; performing a surface treatment process to convert an upper layer of the liner distal to the fin into a conversion layer, the conversion layer comprising an oxide or a nitride of the liner; forming isolation regions on opposing sides of the fin after the surface treatment process; forming a gate dielectric over the conversion layer after forming the isolation regions; and forming a gate electrode over the fin and over the gate dielectric.