FinFET Conformal Layer Vertical Sidewalls Strain Control

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Solution Overview

Problem

Conventional FinFET devices face challenges in achieving uniform gate control and strain, leading to variations in electrical behavior and increased complexity in three-dimensional transistor architectures.

Innovation Solution

The implementation of a FinFET device with a conformal layer having vertical sidewalls parallel to the gate area, which provides uniform gate control and strain, and is formed using techniques like chemical vapor deposition or atomic layer deposition, allowing for a lightly-doped semiconductor material that inhibits out-diffusion and offers tensile or compressive stress.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Length of moving object

If conventional FinFET devices are used, then device size can be shrunk, but uniform gate control and strain are difficult to achieve

Engineering Contradiction:
Improvedevice sizeVSAvoiduniform gate control and strain
Core Design Contradiction:
Length of moving objectVSManufacturing precision

Solution Approach 1:

The device is divided into distinct structural segments: a fin region with the channel, source/drain regions at opposite ends, and a conformal layer that segments the space between source/drain regions. This segmentation allows independent optimization of gate control in the fin region while maintaining strain in the channel region, resolving the contradiction between device shrinkage and uniform control.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the device are given different properties: the fin region provides gate control, the source/drain regions provide electrical contacts, and the conformal layer with vertical sidewalls provides localized strain and mobility enhancement in the channel region. This local differentiation allows each region to optimize its function without compromising overall device performance.

Inventive Principle:
Principle #3Local quality

2Area of moving object

If three-dimensional transistor architectures are implemented, then areal density improves, but device-to-device variation increases

Engineering Contradiction:
Improveareal densityVSAvoiddevice-to-device variation
Core Design Contradiction:
Area of moving objectVSReliability

Solution Approach 1:

The conformal layer is designed with specific geometric parameters (vertical sidewalls, controlled thickness) that can be precisely controlled during fabrication. By changing and optimizing these parameters, the device achieves consistent electrical characteristics across multiple devices, reducing variation while maintaining high areal density through the three-dimensional architecture.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If mobility enhancement is achieved through strain, then electrical performance improves, but gate oxide damage increases

Engineering Contradiction:
Improveelectrical performanceVSAvoidgate oxide damage
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The conformal layer acts as an intermediary structure that introduces strain to the channel region through its vertical sidewalls, enhancing carrier mobility without requiring direct mechanical stress on the gate oxide. This mediator approach allows mobility enhancement while protecting the gate oxide from damage that would occur with more aggressive strain introduction methods.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration enhances mobility, reduces device-to-device variation, and minimizes gate oxide damage, resulting in improved performance and reliability of FinFET devices.

Implementation Method 1

a first conformal layer formed around an embedded portion of the source/drain region, the first conformal layer including a vertical sidewall oriented parallel to the gate area

Methodology Applied
Scientific EffectStrain: Deformation

Data Source

PatentUS9997629B2FinFET with high mobility and strain channel
Publication Date: 2018.06.12 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US9997629B2 patent drawing
  • US9997629B2 patent drawing
  • US9997629B2 patent drawing

AI summary

An integrated circuit device includes a fin having a gate area beneath a gate electrode structure, a source/drain region disposed beyond ends of the fin, and a first conformal layer formed around an embedded portion of the source/drain region. A vertical sidewall of the first conformal layer is oriented parallel to the gate area.