FinFET Contact Air-Gap Structure for Parasitic Capacitance Reduction
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Solution Overview
Problem
Existing semiconductor technologies face issues with parasitic capacitance and bridging (leakage) in advanced technology nodes with smaller feature sizes, such as 20 nm or less, which degrade circuit performance and reliability.
Innovation Solution
The method involves forming FinFET devices with controlled air gaps by etching contact trenches, depositing a glue layer, and filling with conductive material, followed by thermal reflow to create air gaps surrounded by dielectric material, which reduces parasitic capacitance and enhances circuit performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional interconnection structures are used in advanced technology nodes, then circuit integration is achieved, but parasitic capacitance increases and circuit performance degrades
Solution Approach 1:
The patent extracts the harmful dielectric material between contact features and replaces it with air gaps. By removing the solid dielectric material that causes parasitic capacitance and replacing it with air (vacuum), the harmful capacitive coupling between adjacent interconnection structures is eliminated, directly addressing the parasitic capacitance issue in advanced technology nodes
Solution Approach 2:
The patent introduces porous air gap structures between contact features. These air gaps are formed by removing dielectric material and creating void spaces filled with air or vacuum. The porous structure reduces the dielectric constant between adjacent conductors, thereby reducing parasitic capacitance while maintaining electrical isolation
2Productivity
If feature sizes are reduced to 20 nm or less, then device density increases, but parasitic capacitance deteriorates and reliability decreases
Solution Approach 1:
The patent changes the dielectric parameter between contact features from solid dielectric material to air gaps with much lower dielectric constant. This parameter change allows for reduced feature sizes and higher device density while maintaining low parasitic capacitance, as the air gap's low dielectric constant compensates for the reduced spacing between features
3Reliability
If air gaps are introduced to reduce parasitic capacitance, then circuit performance improves, but manufacturing complexity increases
Solution Approach 1:
The patent performs preliminary action by forming the air gaps during the interconnection fabrication process itself, rather than as a separate post-processing step. The air gaps are created by selective removal of dielectric material during the standard damascene or contact formation processes, integrating the air gap formation into the existing manufacturing flow and minimizing additional process complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces parasitic capacitance and improves circuit performance by tuning the air gap formation processes, leading to enhanced reliability and efficiency in interconnection structures.
Implementation Method 1
performing a thermal reflow process, thereby forming air gaps
Data Source
AI summary
The present disclosure provides an integrated circuit (IC) structure. The IC structure includes first and second fins formed on a semiconductor substrate and laterally separated from each other by an isolation feature, the isolation feature formed of a dielectric material that physically contacts the semiconductor substrate; and a contact feature between the first and second fins and extending into the isolation feature thereby defining an air gap vertically between the isolation feature and the contact feature, the dielectric material of the isolation feature extending from the semiconductor substrate to the contact feature.