FinFET Contact-All-Around Structure for Reduced Resistance

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Solution Overview

Problem

As integrated circuits shrink, the contact resistance between metal contact plugs and semiconductor regions in FinFETs increases due to smaller silicide regions, leading to higher electrical contact resistance, which is a severe issue in Fin Field-Effect Transistors.

Innovation Solution

A method is developed to form a contact-all-around structure by recessing STI regions after epitaxy to expose sidewalls of source/drain regions, followed by forming source/drain silicide regions and contact plugs that encircle the epitaxy semiconductor portions, increasing the contact area and reducing resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If integrated circuits are downsized to increase productivity, then productivity is improved, but contact resistance increases due to smaller silicide regions

Engineering Contradiction:
Improveintegrated circuit densityVSAvoidcontact resistance
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The contact structure transitions from a planar contact to a three-dimensional contact-all-around structure. The contact plug extends laterally to encircle the epitaxy semiconductor portion, utilizing the third dimension (circumferential direction) to increase contact area. This dimensional change allows the contact area to scale independently from the fin width, resolving the contradiction between circuit downsizing and contact resistance maintenance.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The contact plug is positioned within a recess that is surrounded by the gate stack and gate spacer, creating a nested structure. The contact-all-around structure nests the contact plug inside the recess, with the contact plug laterally encircling the epitaxy semiconductor portion. This nesting arrangement maximizes the contact area within the limited space available in downsized integrated circuits.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Ease of manufacture

If conventional silicidation process is used, then manufacturing process is simple, but contact area is insufficient leading to high contact resistance

Engineering Contradiction:
Improveprocess simplicityVSAvoidcontact resistance
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The recess is formed prior to the silicidation process, and the metal layer is deposited conformally on the exposed surfaces including the sidewalls of the epitaxy semiconductor portion. This preliminary formation of the recess structure enables the subsequent silicidation to naturally create the contact-all-around structure without requiring additional complex processing steps. The preliminary action of forming the recess prepares the geometry that will lead to the desired contact structure.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The conformal deposition of the metal layer and subsequent silicidation process automatically form the contact-all-around structure on the exposed surfaces. The self-service mechanism utilizes the conformal nature of the deposition and reaction processes to create uniform silicide regions on all exposed surfaces, including the sidewalls, without requiring additional patterning or etching steps. The process self-organizes to create the desired three-dimensional contact structure.

Inventive Principle:
Principle #25Self-service

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively reduces the source/drain contact resistance by increasing the contact area and optimizing the contact structure, addressing the challenge of high contact resistance in FinFETs as they scale down.

Implementation Method 1

performing an annealing, so that the metal layer reacts with the semiconductor regions to form the silicide regions

Methodology Applied
Scientific EffectAnnealing: Annealing

Implementation Method 2

the metal layer reacts with the semiconductor regions to form the silicide regions

Methodology Applied
Scientific EffectChemical reaction: Chemical Bonding

Implementation Method 3

performing an epitaxy to grow an epitaxy semiconductor region

Methodology Applied
Scientific EffectEpitaxy: Epitaxy

Data Source

PatentUS9911830B2FinFETs with contact-all-around
Publication Date: 2018.03.06 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US9911830B2 patent drawing
  • US9911830B2 patent drawing
  • US9911830B2 patent drawing

AI summary

An integrated circuit structure includes a semiconductor substrate, a semiconductor fin over the semiconductor substrate, a gate stack on a top surface and a sidewall of the semiconductor fin, a source/drain region on a side of the gate stack, and a contact plug encircling a portion of the source/drain region.